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AArch64
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[AArch64][GlobalISel] Make LR livein to entry in llvm.returnaddress selection
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2020-05-11 11:32:12 -07:00 |
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AMDGPU
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AMDGPU/GlobalISel: Remove -global-isel-abort=0 from tests
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2020-05-10 17:19:47 -04:00 |
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ARC
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ARM
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Correctly modify the CFG in IfConverter, and then remove the
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2020-05-07 18:17:07 -04:00 |
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AVR
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[AVR] Do not place functions in .progmem.data
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2020-04-20 13:56:38 +02:00 |
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BPF
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BPF: fix a CORE optimization bug
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2020-04-20 19:54:51 -07:00 |
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Generic
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[MachineDebugify] Insert synthetic DBG_VALUE instructions
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2020-04-22 17:03:39 -07:00 |
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Hexagon
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[ModuloSchedule] Fix epilogue peeling with illegal phi.
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2020-05-07 10:04:05 -07:00 |
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Inputs
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Lanai
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MIR
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[AMDGPU] Avoid hard-coded line numbers in error message checks
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2020-04-23 21:06:09 +01:00 |
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MSP430
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Mips
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[SelectionDAGBuilder] Stop setting alignment to one for hidden sret values
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2020-05-04 14:44:39 +01:00 |
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NVPTX
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[llvm] Fix missing FileCheck directive colons
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2020-04-06 09:59:08 -06:00 |
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PowerPC
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Move PowerPC specific test under PowerPC directive to fix build break
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2020-05-11 20:05:05 +00:00 |
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RISCV
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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SPARC
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SystemZ
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[SystemZ] Fix/optimize vec_load_len and related intrinsics
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2020-05-06 21:15:58 +02:00 |
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Thumb
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[ARM] Don't shrink STM if it would cause an unknown base register store
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2020-04-22 14:50:42 +01:00 |
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Thumb2
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[ARM] Convert VDUPLANE to VDUP under MVE
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2020-05-09 18:58:13 +01:00 |
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VE
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[VE] Update branch instructions
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2020-04-28 09:41:01 +02:00 |
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WebAssembly
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[WebAssembly] Add wasm-specific vector shuffle builtin and intrinsic
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2020-05-11 10:01:55 -07:00 |
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WinCFGuard
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WinEH
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X86
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[x86][seses] Introduce SESES pass for LVI
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2020-05-11 09:34:37 -07:00 |
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XCore
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