Silviu Baranga ddc67a7655 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. ... llvm-svn: 156609		2012-05-11 09:28:27 +00:00
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ARM	Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.	2012-05-11 09:28:27 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	Add disassembler to MIPS.	2012-04-17 18:03:21 +00:00
X86	Missed some register numbers.	2012-04-27 12:21:46 +00:00