forked from OSchip/llvm-project
319 lines
12 KiB
LLVM
319 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX
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; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX512
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; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,-vzeroupper | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=DISABLE-VZ
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; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=BDVER2
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; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=BTVER2
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declare i32 @foo()
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declare <4 x float> @do_sse(<4 x float>)
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declare <8 x float> @do_avx(<8 x float>)
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declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
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@x = common global <4 x float> zeroinitializer, align 16
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@g = common global <8 x float> zeroinitializer, align 32
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;; Basic checking - don't emit any vzeroupper instruction
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define <4 x float> @test00(<4 x float> %a, <4 x float> %b) nounwind {
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; ALL-LABEL: test00:
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; ALL: # %bb.0:
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; ALL-NEXT: pushq %rax
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; ALL-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; ALL-NEXT: callq do_sse
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; ALL-NEXT: popq %rax
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; ALL-NEXT: retq
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%add.i = fadd <4 x float> %a, %b
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%call3 = call <4 x float> @do_sse(<4 x float> %add.i) nounwind
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ret <4 x float> %call3
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}
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;; Check parameter 256-bit parameter passing
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define <8 x float> @test01(<4 x float> %a, <4 x float> %b, <8 x float> %c) nounwind {
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; VZ-LABEL: test01:
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; VZ: # %bb.0:
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; VZ-NEXT: subq $56, %rsp
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; VZ-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
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; VZ-NEXT: vmovaps {{.*}}(%rip), %xmm0
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; VZ-NEXT: vzeroupper
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; VZ-NEXT: callq do_sse
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; VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; VZ-NEXT: callq do_sse
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; VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; VZ-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
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; VZ-NEXT: addq $56, %rsp
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; VZ-NEXT: retq
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;
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; DISABLE-VZ-LABEL: test01:
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; DISABLE-VZ: # %bb.0:
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; DISABLE-VZ-NEXT: subq $56, %rsp
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; DISABLE-VZ-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
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; DISABLE-VZ-NEXT: vmovaps {{.*}}(%rip), %xmm0
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; DISABLE-VZ-NEXT: callq do_sse
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; DISABLE-VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; DISABLE-VZ-NEXT: callq do_sse
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; DISABLE-VZ-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; DISABLE-VZ-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
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; DISABLE-VZ-NEXT: addq $56, %rsp
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; DISABLE-VZ-NEXT: retq
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;
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; BDVER2-LABEL: test01:
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; BDVER2: # %bb.0:
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; BDVER2-NEXT: subq $56, %rsp
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; BDVER2-NEXT: vmovaps {{.*}}(%rip), %xmm0
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; BDVER2-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
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; BDVER2-NEXT: vzeroupper
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; BDVER2-NEXT: callq do_sse
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; BDVER2-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; BDVER2-NEXT: callq do_sse
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; BDVER2-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; BDVER2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
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; BDVER2-NEXT: addq $56, %rsp
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; BDVER2-NEXT: retq
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;
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; BTVER2-LABEL: test01:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: subq $56, %rsp
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; BTVER2-NEXT: vmovaps {{.*}}(%rip), %xmm0
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; BTVER2-NEXT: vmovups %ymm2, (%rsp) # 32-byte Spill
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; BTVER2-NEXT: callq do_sse
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; BTVER2-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; BTVER2-NEXT: callq do_sse
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; BTVER2-NEXT: vmovaps %xmm0, {{.*}}(%rip)
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; BTVER2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload
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; BTVER2-NEXT: addq $56, %rsp
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; BTVER2-NEXT: retq
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; DISABLE-VZ # %bb.0:
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%tmp = load <4 x float>, <4 x float>* @x, align 16
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%call = tail call <4 x float> @do_sse(<4 x float> %tmp) nounwind
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store <4 x float> %call, <4 x float>* @x, align 16
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%call2 = tail call <4 x float> @do_sse(<4 x float> %call) nounwind
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store <4 x float> %call2, <4 x float>* @x, align 16
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ret <8 x float> %c
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}
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;; Check that vzeroupper is emitted for tail calls.
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define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind {
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; VZ-LABEL: test02:
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; VZ: # %bb.0:
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; VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; VZ-NEXT: vzeroupper
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; VZ-NEXT: jmp do_sse # TAILCALL
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;
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; DISABLE-VZ-LABEL: test02:
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; DISABLE-VZ: # %bb.0:
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; DISABLE-VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; DISABLE-VZ-NEXT: jmp do_sse # TAILCALL
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;
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; BDVER2-LABEL: test02:
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; BDVER2: # %bb.0:
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; BDVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; BDVER2-NEXT: vzeroupper
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; BDVER2-NEXT: jmp do_sse # TAILCALL
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;
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; BTVER2-LABEL: test02:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; BTVER2-NEXT: jmp do_sse # TAILCALL
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%add.i = fadd <8 x float> %a, %b
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%add.low = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %add.i, i8 0)
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%call3 = tail call <4 x float> @do_sse(<4 x float> %add.low) nounwind
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ret <4 x float> %call3
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}
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;; Test the pass convergence and also that vzeroupper is only issued when necessary,
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;; for this function it should be only once
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define <4 x float> @test03(<4 x float> %a, <4 x float> %b) nounwind {
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; VZ-LABEL: test03:
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; VZ: # %bb.0: # %entry
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; VZ-NEXT: pushq %rbx
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; VZ-NEXT: subq $16, %rsp
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; VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; VZ-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
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; VZ-NEXT: .p2align 4, 0x90
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; VZ-NEXT: .LBB3_1: # %while.cond
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; VZ-NEXT: # =>This Inner Loop Header: Depth=1
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; VZ-NEXT: callq foo
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; VZ-NEXT: testl %eax, %eax
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; VZ-NEXT: jne .LBB3_1
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; VZ-NEXT: # %bb.2: # %for.body.preheader
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; VZ-NEXT: movl $4, %ebx
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; VZ-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
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; VZ-NEXT: .p2align 4, 0x90
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; VZ-NEXT: .LBB3_3: # %for.body
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; VZ-NEXT: # =>This Inner Loop Header: Depth=1
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; VZ-NEXT: callq do_sse
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; VZ-NEXT: callq do_sse
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; VZ-NEXT: vmovaps g+{{.*}}(%rip), %xmm0
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; VZ-NEXT: callq do_sse
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; VZ-NEXT: decl %ebx
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; VZ-NEXT: jne .LBB3_3
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; VZ-NEXT: # %bb.4: # %for.end
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; VZ-NEXT: addq $16, %rsp
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; VZ-NEXT: popq %rbx
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; VZ-NEXT: retq
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;
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; DISABLE-VZ-LABEL: test03:
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; DISABLE-VZ: # %bb.0: # %entry
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; DISABLE-VZ-NEXT: pushq %rbx
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; DISABLE-VZ-NEXT: subq $16, %rsp
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; DISABLE-VZ-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; DISABLE-VZ-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
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; DISABLE-VZ-NEXT: .p2align 4, 0x90
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; DISABLE-VZ-NEXT: .LBB3_1: # %while.cond
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; DISABLE-VZ-NEXT: # =>This Inner Loop Header: Depth=1
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; DISABLE-VZ-NEXT: callq foo
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; DISABLE-VZ-NEXT: testl %eax, %eax
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; DISABLE-VZ-NEXT: jne .LBB3_1
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; DISABLE-VZ-NEXT: # %bb.2: # %for.body.preheader
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; DISABLE-VZ-NEXT: movl $4, %ebx
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; DISABLE-VZ-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
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; DISABLE-VZ-NEXT: .p2align 4, 0x90
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; DISABLE-VZ-NEXT: .LBB3_3: # %for.body
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; DISABLE-VZ-NEXT: # =>This Inner Loop Header: Depth=1
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; DISABLE-VZ-NEXT: callq do_sse
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; DISABLE-VZ-NEXT: callq do_sse
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; DISABLE-VZ-NEXT: vmovaps g+{{.*}}(%rip), %xmm0
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; DISABLE-VZ-NEXT: callq do_sse
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; DISABLE-VZ-NEXT: decl %ebx
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; DISABLE-VZ-NEXT: jne .LBB3_3
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; DISABLE-VZ-NEXT: # %bb.4: # %for.end
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; DISABLE-VZ-NEXT: addq $16, %rsp
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; DISABLE-VZ-NEXT: popq %rbx
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; DISABLE-VZ-NEXT: retq
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;
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; BDVER2-LABEL: test03:
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; BDVER2: # %bb.0: # %entry
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; BDVER2-NEXT: pushq %rbx
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; BDVER2-NEXT: subq $16, %rsp
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; BDVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; BDVER2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
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; BDVER2-NEXT: .p2align 4, 0x90
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; BDVER2-NEXT: .LBB3_1: # %while.cond
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; BDVER2-NEXT: # =>This Inner Loop Header: Depth=1
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; BDVER2-NEXT: callq foo
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; BDVER2-NEXT: testl %eax, %eax
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; BDVER2-NEXT: jne .LBB3_1
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; BDVER2-NEXT: # %bb.2: # %for.body.preheader
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; BDVER2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
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; BDVER2-NEXT: movl $4, %ebx
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; BDVER2-NEXT: .p2align 4, 0x90
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; BDVER2-NEXT: .LBB3_3: # %for.body
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; BDVER2-NEXT: # =>This Inner Loop Header: Depth=1
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; BDVER2-NEXT: callq do_sse
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; BDVER2-NEXT: callq do_sse
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; BDVER2-NEXT: vmovaps g+{{.*}}(%rip), %xmm0
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; BDVER2-NEXT: callq do_sse
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; BDVER2-NEXT: decl %ebx
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; BDVER2-NEXT: jne .LBB3_3
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; BDVER2-NEXT: # %bb.4: # %for.end
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; BDVER2-NEXT: addq $16, %rsp
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; BDVER2-NEXT: popq %rbx
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; BDVER2-NEXT: retq
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;
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; BTVER2-LABEL: test03:
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; BTVER2: # %bb.0: # %entry
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; BTVER2-NEXT: pushq %rbx
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; BTVER2-NEXT: subq $16, %rsp
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; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; BTVER2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
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; BTVER2-NEXT: .p2align 4, 0x90
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; BTVER2-NEXT: .LBB3_1: # %while.cond
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; BTVER2-NEXT: # =>This Inner Loop Header: Depth=1
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; BTVER2-NEXT: callq foo
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; BTVER2-NEXT: testl %eax, %eax
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; BTVER2-NEXT: jne .LBB3_1
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; BTVER2-NEXT: # %bb.2: # %for.body.preheader
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; BTVER2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
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; BTVER2-NEXT: movl $4, %ebx
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; BTVER2-NEXT: .p2align 4, 0x90
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; BTVER2-NEXT: .LBB3_3: # %for.body
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; BTVER2-NEXT: # =>This Inner Loop Header: Depth=1
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; BTVER2-NEXT: callq do_sse
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; BTVER2-NEXT: callq do_sse
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; BTVER2-NEXT: vmovaps g+{{.*}}(%rip), %xmm0
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; BTVER2-NEXT: callq do_sse
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; BTVER2-NEXT: decl %ebx
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; BTVER2-NEXT: jne .LBB3_3
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; BTVER2-NEXT: # %bb.4: # %for.end
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; BTVER2-NEXT: addq $16, %rsp
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; BTVER2-NEXT: popq %rbx
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; BTVER2-NEXT: retq
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entry:
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%add.i = fadd <4 x float> %a, %b
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br label %while.cond
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while.cond:
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%call = tail call i32 @foo()
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%tobool = icmp eq i32 %call, 0
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br i1 %tobool, label %for.body, label %while.cond
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for.body:
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%i.018 = phi i32 [ 0, %while.cond ], [ %1, %for.body ]
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%c.017 = phi <4 x float> [ %add.i, %while.cond ], [ %call14, %for.body ]
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%call5 = tail call <4 x float> @do_sse(<4 x float> %c.017) nounwind
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%call7 = tail call <4 x float> @do_sse(<4 x float> %call5) nounwind
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%tmp11 = load <8 x float>, <8 x float>* @g, align 32
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %tmp11, i8 1) nounwind
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%call14 = tail call <4 x float> @do_sse(<4 x float> %0) nounwind
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%1 = add nsw i32 %i.018, 1
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%exitcond = icmp eq i32 %1, 4
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret <4 x float> %call14
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}
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;; Check that we also perform vzeroupper when we return from a function.
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define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind {
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; VZ-LABEL: test04:
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; VZ: # %bb.0:
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; VZ-NEXT: pushq %rax
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; VZ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; VZ-NEXT: callq do_avx
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; VZ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; VZ-NEXT: popq %rax
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; VZ-NEXT: vzeroupper
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; VZ-NEXT: retq
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;
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; DISABLE-VZ-LABEL: test04:
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; DISABLE-VZ: # %bb.0:
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; DISABLE-VZ-NEXT: pushq %rax
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; DISABLE-VZ-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; DISABLE-VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; DISABLE-VZ-NEXT: callq do_avx
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; DISABLE-VZ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; DISABLE-VZ-NEXT: popq %rax
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; DISABLE-VZ-NEXT: retq
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;
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; BDVER2-LABEL: test04:
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; BDVER2: # %bb.0:
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; BDVER2-NEXT: pushq %rax
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; BDVER2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; BDVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; BDVER2-NEXT: callq do_avx
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; BDVER2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; BDVER2-NEXT: popq %rax
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; BDVER2-NEXT: vzeroupper
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; BDVER2-NEXT: retq
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;
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; BTVER2-LABEL: test04:
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; BTVER2: # %bb.0:
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; BTVER2-NEXT: pushq %rax
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; BTVER2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
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; BTVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; BTVER2-NEXT: callq do_avx
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; BTVER2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; BTVER2-NEXT: popq %rax
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; BTVER2-NEXT: retq
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%shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%call = call <8 x float> @do_avx(<8 x float> %shuf) nounwind
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%shuf2 = shufflevector <8 x float> %call, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x float> %shuf2
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}
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