forked from OSchip/llvm-project
152 lines
5.4 KiB
C++
152 lines
5.4 KiB
C++
//===-- AMDGPUTargetStreamer.h - AMDGPU Target Streamer --------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
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#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
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#include "AMDKernelCodeT.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/AMDGPUMetadata.h"
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#include "llvm/Support/AMDHSAKernelDescriptor.h"
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namespace llvm {
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#include "AMDGPUPTNote.h"
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class DataLayout;
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class Function;
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class MCELFStreamer;
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class MCSymbol;
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class MDNode;
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class Module;
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class Type;
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class AMDGPUTargetStreamer : public MCTargetStreamer {
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protected:
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MCContext &getContext() const { return Streamer.getContext(); }
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/// \returns Equivalent EF_AMDGPU_MACH_* value for given \p GPU name.
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unsigned getMACH(StringRef GPU) const;
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public:
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/// \returns Equivalent GPU name for an EF_AMDGPU_MACH_* value.
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static const char *getMachName(unsigned Mach);
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AMDGPUTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
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virtual void EmitDirectiveAMDGCNTarget(StringRef Target) = 0;
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virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
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uint32_t Minor) = 0;
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virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
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uint32_t Stepping,
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StringRef VendorName,
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StringRef ArchName) = 0;
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virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) = 0;
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virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) = 0;
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/// \returns True on success, false on failure.
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virtual bool EmitISAVersion(StringRef IsaVersionString) = 0;
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/// \returns True on success, false on failure.
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virtual bool EmitHSAMetadata(StringRef HSAMetadataString);
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/// \returns True on success, false on failure.
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virtual bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) = 0;
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/// \returns True on success, false on failure.
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virtual bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) = 0;
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virtual void EmitAmdhsaKernelDescriptor(
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const MCSubtargetInfo &STI, StringRef KernelName,
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const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
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uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
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bool ReserveXNACK) = 0;
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};
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class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
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formatted_raw_ostream &OS;
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public:
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AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
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void EmitDirectiveAMDGCNTarget(StringRef Target) override;
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void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
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uint32_t Minor) override;
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void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
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uint32_t Stepping, StringRef VendorName,
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StringRef ArchName) override;
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void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
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void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
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/// \returns True on success, false on failure.
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bool EmitISAVersion(StringRef IsaVersionString) override;
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/// \returns True on success, false on failure.
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bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
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/// \returns True on success, false on failure.
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bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
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void EmitAmdhsaKernelDescriptor(
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const MCSubtargetInfo &STI, StringRef KernelName,
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const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
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uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
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bool ReserveXNACK) override;
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};
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class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
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MCStreamer &Streamer;
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void EmitAMDGPUNote(const MCExpr *DescSize, unsigned NoteType,
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function_ref<void(MCELFStreamer &)> EmitDesc);
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public:
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AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
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MCELFStreamer &getStreamer();
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void EmitDirectiveAMDGCNTarget(StringRef Target) override;
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void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
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uint32_t Minor) override;
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void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
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uint32_t Stepping, StringRef VendorName,
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StringRef ArchName) override;
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void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
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void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
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/// \returns True on success, false on failure.
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bool EmitISAVersion(StringRef IsaVersionString) override;
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/// \returns True on success, false on failure.
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bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
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/// \returns True on success, false on failure.
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bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
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void EmitAmdhsaKernelDescriptor(
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const MCSubtargetInfo &STI, StringRef KernelName,
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const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
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uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
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bool ReserveXNACK) override;
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};
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}
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#endif
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