forked from OSchip/llvm-project
283 lines
8.8 KiB
C++
283 lines
8.8 KiB
C++
//===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the RISCV target.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "Utils/RISCVMatInt.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-isel"
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// RISCV-specific code to select RISCV machine instructions for
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// SelectionDAG operations.
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namespace {
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class RISCVDAGToDAGISel final : public SelectionDAGISel {
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const RISCVSubtarget *Subtarget;
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public:
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explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
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: SelectionDAGISel(TargetMachine) {}
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StringRef getPassName() const override {
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return "RISCV DAG->DAG Pattern Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<RISCVSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void PostprocessISelDAG() override;
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void Select(SDNode *Node) override;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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bool SelectAddrFI(SDValue Addr, SDValue &Base);
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// Include the pieces autogenerated from the target description.
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#include "RISCVGenDAGISel.inc"
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private:
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void doPeepholeLoadStoreADDI();
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};
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}
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void RISCVDAGToDAGISel::PostprocessISelDAG() {
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doPeepholeLoadStoreADDI();
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}
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static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
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MVT XLenVT) {
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RISCVMatInt::InstSeq Seq;
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RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq);
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SDNode *Result;
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SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
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for (RISCVMatInt::Inst &Inst : Seq) {
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SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
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if (Inst.Opc == RISCV::LUI)
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Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
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else
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Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);
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// Only the first instruction has X0 as its source.
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SrcReg = SDValue(Result, 0);
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}
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return Result;
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}
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// Returns true if the Node is an ISD::AND with a constant argument. If so,
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// set Mask to that constant value.
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static bool isConstantMask(SDNode *Node, uint64_t &Mask) {
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if (Node->getOpcode() == ISD::AND &&
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Node->getOperand(1).getOpcode() == ISD::Constant) {
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Mask = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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return true;
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}
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return false;
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}
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void RISCVDAGToDAGISel::Select(SDNode *Node) {
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// If we have a custom node, we have already selected.
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if (Node->isMachineOpcode()) {
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LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
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Node->setNodeId(-1);
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return;
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}
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// Instruction Selection not handled by the auto-generated tablegen selection
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// should be handled here.
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unsigned Opcode = Node->getOpcode();
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MVT XLenVT = Subtarget->getXLenVT();
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SDLoc DL(Node);
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EVT VT = Node->getValueType(0);
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switch (Opcode) {
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case ISD::Constant: {
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auto ConstNode = cast<ConstantSDNode>(Node);
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if (VT == XLenVT && ConstNode->isNullValue()) {
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SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
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RISCV::X0, XLenVT);
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ReplaceNode(Node, New.getNode());
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return;
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}
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int64_t Imm = ConstNode->getSExtValue();
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if (XLenVT == MVT::i64) {
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ReplaceNode(Node, selectImm(CurDAG, SDLoc(Node), Imm, XLenVT));
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return;
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}
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break;
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}
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case ISD::FrameIndex: {
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SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT);
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
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ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
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return;
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}
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case ISD::SRL: {
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if (!Subtarget->is64Bit())
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break;
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SDValue Op0 = Node->getOperand(0);
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SDValue Op1 = Node->getOperand(1);
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uint64_t Mask;
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// Match (srl (and val, mask), imm) where the result would be a
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// zero-extended 32-bit integer. i.e. the mask is 0xffffffff or the result
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// is equivalent to this (SimplifyDemandedBits may have removed lower bits
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// from the mask that aren't necessary due to the right-shifting).
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if (Op1.getOpcode() == ISD::Constant &&
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isConstantMask(Op0.getNode(), Mask)) {
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uint64_t ShAmt = cast<ConstantSDNode>(Op1.getNode())->getZExtValue();
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if ((Mask | maskTrailingOnes<uint64_t>(ShAmt)) == 0xffffffff) {
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SDValue ShAmtVal =
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CurDAG->getTargetConstant(ShAmt, SDLoc(Node), XLenVT);
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CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0.getOperand(0),
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ShAmtVal);
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return;
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}
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}
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}
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}
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// Select the default instruction.
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SelectCode(Node);
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}
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bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
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const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
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switch (ConstraintID) {
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_m:
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// We just support simple memory operands that have a single address
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// operand and need no special handling.
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OutOps.push_back(Op);
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return false;
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default:
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break;
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}
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return true;
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}
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bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr, SDValue &Base) {
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if (auto FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());
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return true;
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}
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return false;
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}
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// Merge an ADDI into the offset of a load/store instruction where possible.
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// (load (add base, off), 0) -> (load base, off)
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// (store val, (add base, off)) -> (store val, base, off)
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void RISCVDAGToDAGISel::doPeepholeLoadStoreADDI() {
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SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
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++Position;
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while (Position != CurDAG->allnodes_begin()) {
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SDNode *N = &*--Position;
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// Skip dead nodes and any non-machine opcodes.
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if (N->use_empty() || !N->isMachineOpcode())
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continue;
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int OffsetOpIdx;
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int BaseOpIdx;
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// Only attempt this optimisation for I-type loads and S-type stores.
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switch (N->getMachineOpcode()) {
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default:
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continue;
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case RISCV::LB:
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case RISCV::LH:
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case RISCV::LW:
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case RISCV::LBU:
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case RISCV::LHU:
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case RISCV::LWU:
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case RISCV::LD:
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case RISCV::FLW:
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case RISCV::FLD:
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BaseOpIdx = 0;
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OffsetOpIdx = 1;
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break;
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case RISCV::SB:
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case RISCV::SH:
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case RISCV::SW:
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case RISCV::SD:
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case RISCV::FSW:
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case RISCV::FSD:
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BaseOpIdx = 1;
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OffsetOpIdx = 2;
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break;
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}
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// Currently, the load/store offset must be 0 to be considered for this
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// peephole optimisation.
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if (!isa<ConstantSDNode>(N->getOperand(OffsetOpIdx)) ||
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N->getConstantOperandVal(OffsetOpIdx) != 0)
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continue;
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SDValue Base = N->getOperand(BaseOpIdx);
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// If the base is an ADDI, we can merge it in to the load/store.
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if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI)
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continue;
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SDValue ImmOperand = Base.getOperand(1);
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if (auto Const = dyn_cast<ConstantSDNode>(ImmOperand)) {
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ImmOperand = CurDAG->getTargetConstant(
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Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType());
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} else if (auto GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) {
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ImmOperand = CurDAG->getTargetGlobalAddress(
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GA->getGlobal(), SDLoc(ImmOperand), ImmOperand.getValueType(),
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GA->getOffset(), GA->getTargetFlags());
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} else {
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continue;
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}
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LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
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LLVM_DEBUG(Base->dump(CurDAG));
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LLVM_DEBUG(dbgs() << "\nN: ");
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LLVM_DEBUG(N->dump(CurDAG));
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LLVM_DEBUG(dbgs() << "\n");
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// Modify the offset operand of the load/store.
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if (BaseOpIdx == 0) // Load
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CurDAG->UpdateNodeOperands(N, Base.getOperand(0), ImmOperand,
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N->getOperand(2));
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else // Store
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CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0),
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ImmOperand, N->getOperand(3));
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// The add-immediate may now be dead, in which case remove it.
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if (Base.getNode()->use_empty())
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CurDAG->RemoveDeadNode(Base.getNode());
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}
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}
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// This pass converts a legalized DAG into a RISCV-specific DAG, ready
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// for instruction scheduling.
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FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM) {
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return new RISCVDAGToDAGISel(TM);
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}
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