forked from OSchip/llvm-project
348 lines
10 KiB
LLVM
348 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -o - -mtriple=i686-unknown-unknown %s | FileCheck %s --check-prefixes=ALL,X32
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; RUN: llc -o - -mtriple=x86_64-unknown-unknown %s | FileCheck %s --check-prefixes=ALL,X64
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;
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; Test patterns that require preserving and restoring flags.
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@b = common global i8 0, align 1
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@c = common global i32 0, align 4
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@a = common global i8 0, align 1
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@d = common global i8 0, align 1
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@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
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declare void @external(i32)
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; A test that re-uses flags in interesting ways due to volatile accesses.
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; Specifically, the first increment's flags are reused for the branch despite
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; being clobbered by the second increment.
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define i32 @test1() nounwind {
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; X32-LABEL: test1:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movb b, %cl
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; X32-NEXT: movl %ecx, %eax
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; X32-NEXT: incb %al
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; X32-NEXT: movb %al, b
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; X32-NEXT: incl c
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; X32-NEXT: sete %dl
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; X32-NEXT: movb a, %ah
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; X32-NEXT: movb %ah, %ch
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; X32-NEXT: incb %ch
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; X32-NEXT: cmpb %cl, %ah
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; X32-NEXT: sete d
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; X32-NEXT: movb %ch, a
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; X32-NEXT: testb %dl, %dl
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; X32-NEXT: jne .LBB0_2
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; X32-NEXT: # %bb.1: # %if.then
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; X32-NEXT: movsbl %al, %eax
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll external
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; X32-NEXT: addl $4, %esp
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; X32-NEXT: .LBB0_2: # %if.end
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %rax
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; X64-NEXT: movb {{.*}}(%rip), %cl
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; X64-NEXT: leal 1(%rcx), %eax
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; X64-NEXT: movb %al, {{.*}}(%rip)
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; X64-NEXT: incl {{.*}}(%rip)
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; X64-NEXT: sete %dl
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; X64-NEXT: movb {{.*}}(%rip), %sil
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; X64-NEXT: leal 1(%rsi), %edi
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; X64-NEXT: cmpb %cl, %sil
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; X64-NEXT: sete {{.*}}(%rip)
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; X64-NEXT: movb %dil, {{.*}}(%rip)
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; X64-NEXT: testb %dl, %dl
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; X64-NEXT: jne .LBB0_2
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; X64-NEXT: # %bb.1: # %if.then
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; X64-NEXT: movsbl %al, %edi
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; X64-NEXT: callq external
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; X64-NEXT: .LBB0_2: # %if.end
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: popq %rcx
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; X64-NEXT: retq
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entry:
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%bval = load i8, i8* @b
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%inc = add i8 %bval, 1
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store volatile i8 %inc, i8* @b
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%cval = load volatile i32, i32* @c
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%inc1 = add nsw i32 %cval, 1
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store volatile i32 %inc1, i32* @c
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%aval = load volatile i8, i8* @a
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%inc2 = add i8 %aval, 1
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store volatile i8 %inc2, i8* @a
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%cmp = icmp eq i8 %aval, %bval
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%conv5 = zext i1 %cmp to i8
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store i8 %conv5, i8* @d
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%tobool = icmp eq i32 %inc1, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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%conv6 = sext i8 %inc to i32
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call void @external(i32 %conv6)
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br label %if.end
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if.end:
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ret i32 0
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}
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; Preserve increment flags across a call.
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define i32 @test2(i32* %ptr) nounwind {
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; X32-LABEL: test2:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %ebx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: incl (%eax)
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; X32-NEXT: setne %bl
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; X32-NEXT: pushl $42
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; X32-NEXT: calll external
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; X32-NEXT: addl $4, %esp
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; X32-NEXT: testb %bl, %bl
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; X32-NEXT: jne .LBB1_2
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; X32-NEXT: # %bb.1: # %then
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; X32-NEXT: movl $64, %eax
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; X32-NEXT: popl %ebx
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; X32-NEXT: retl
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; X32-NEXT: .LBB1_2: # %else
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: popl %ebx
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; X32-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %rbx
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; X64-NEXT: incl (%rdi)
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; X64-NEXT: setne %bl
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; X64-NEXT: movl $42, %edi
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; X64-NEXT: callq external
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; X64-NEXT: testb %bl, %bl
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; X64-NEXT: jne .LBB1_2
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; X64-NEXT: # %bb.1: # %then
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; X64-NEXT: movl $64, %eax
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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; X64-NEXT: .LBB1_2: # %else
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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entry:
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%val = load i32, i32* %ptr
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%inc = add i32 %val, 1
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store i32 %inc, i32* %ptr
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%cmp = icmp eq i32 %inc, 0
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call void @external(i32 42)
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br i1 %cmp, label %then, label %else
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then:
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ret i32 64
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else:
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ret i32 0
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}
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declare void @external_a()
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declare void @external_b()
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; This lowers to a conditional tail call instead of a conditional branch. This
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; is tricky because we can only do this from a leaf function, and so we have to
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; use volatile stores similar to test1 to force the save and restore of
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; a condition without calling another function. We then set up subsequent calls
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; in tail position.
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define void @test_tail_call(i32* %ptr) nounwind optsize {
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; X32-LABEL: test_tail_call:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: incl (%eax)
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; X32-NEXT: setne %al
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; X32-NEXT: incb a
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; X32-NEXT: sete d
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; X32-NEXT: testb %al, %al
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; X32-NEXT: jne external_b # TAILCALL
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; X32-NEXT: # %bb.1: # %then
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; X32-NEXT: jmp external_a # TAILCALL
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;
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; X64-LABEL: test_tail_call:
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; X64: # %bb.0: # %entry
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; X64-NEXT: incl (%rdi)
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; X64-NEXT: setne %al
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; X64-NEXT: incb {{.*}}(%rip)
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; X64-NEXT: sete {{.*}}(%rip)
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; X64-NEXT: testb %al, %al
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; X64-NEXT: jne external_b # TAILCALL
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; X64-NEXT: # %bb.1: # %then
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; X64-NEXT: jmp external_a # TAILCALL
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entry:
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%val = load i32, i32* %ptr
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%inc = add i32 %val, 1
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store i32 %inc, i32* %ptr
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%cmp = icmp eq i32 %inc, 0
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%aval = load volatile i8, i8* @a
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%inc2 = add i8 %aval, 1
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store volatile i8 %inc2, i8* @a
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%cmp2 = icmp eq i8 %inc2, 0
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%conv5 = zext i1 %cmp2 to i8
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store i8 %conv5, i8* @d
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br i1 %cmp, label %then, label %else
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then:
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tail call void @external_a()
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ret void
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else:
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tail call void @external_b()
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ret void
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}
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; Test a function that gets special select lowering into CFG with copied EFLAGS
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; threaded across the CFG. This requires our EFLAGS copy rewriting to handle
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; cross-block rewrites in at least some narrow cases.
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define void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, i8* %ptr1, i32* %ptr2, i32 %x) nounwind {
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; X32-LABEL: PR37100:
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; X32: # %bb.0: # %bb
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; X32-NEXT: pushl %ebp
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; X32-NEXT: pushl %ebx
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp
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; X32-NEXT: movb {{[0-9]+}}(%esp), %ch
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: jmp .LBB3_1
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB3_5: # %bb1
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; X32-NEXT: # in Loop: Header=BB3_1 Depth=1
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; X32-NEXT: movl %esi, %eax
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; X32-NEXT: cltd
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; X32-NEXT: idivl %edi
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; X32-NEXT: .LBB3_1: # %bb1
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: movsbl %cl, %eax
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; X32-NEXT: movl %eax, %edx
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; X32-NEXT: sarl $31, %edx
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; X32-NEXT: cmpl %eax, {{[0-9]+}}(%esp)
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: sbbl %edx, %eax
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; X32-NEXT: setl %al
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; X32-NEXT: setl %dl
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; X32-NEXT: movzbl %dl, %edi
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; X32-NEXT: negl %edi
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; X32-NEXT: testb %al, %al
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; X32-NEXT: jne .LBB3_3
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; X32-NEXT: # %bb.2: # %bb1
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; X32-NEXT: # in Loop: Header=BB3_1 Depth=1
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; X32-NEXT: movb %ch, %cl
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; X32-NEXT: .LBB3_3: # %bb1
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; X32-NEXT: # in Loop: Header=BB3_1 Depth=1
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; X32-NEXT: movb %cl, (%ebp)
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; X32-NEXT: movl (%ebx), %edx
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; X32-NEXT: testb %al, %al
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; X32-NEXT: jne .LBB3_5
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; X32-NEXT: # %bb.4: # %bb1
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; X32-NEXT: # in Loop: Header=BB3_1 Depth=1
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; X32-NEXT: movl %edx, %edi
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; X32-NEXT: jmp .LBB3_5
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;
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; X64-LABEL: PR37100:
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; X64: # %bb.0: # %bb
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; X64-NEXT: movq %rdx, %rsi
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; X64-NEXT: movl {{[0-9]+}}(%rsp), %r10d
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; X64-NEXT: movzbl %cl, %r11d
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; X64-NEXT: .p2align 4, 0x90
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; X64-NEXT: .LBB3_1: # %bb1
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; X64-NEXT: # =>This Inner Loop Header: Depth=1
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; X64-NEXT: movsbq %dil, %rax
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; X64-NEXT: xorl %ecx, %ecx
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; X64-NEXT: cmpq %rax, %rsi
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; X64-NEXT: setl %cl
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; X64-NEXT: negl %ecx
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; X64-NEXT: cmpq %rax, %rsi
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; X64-NEXT: movzbl %al, %edi
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; X64-NEXT: cmovgel %r11d, %edi
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; X64-NEXT: movb %dil, (%r8)
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; X64-NEXT: cmovgel (%r9), %ecx
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; X64-NEXT: movl %r10d, %eax
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; X64-NEXT: cltd
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; X64-NEXT: idivl %ecx
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; X64-NEXT: jmp .LBB3_1
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bb:
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br label %bb1
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bb1:
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%tmp = phi i8 [ %tmp8, %bb1 ], [ %arg1, %bb ]
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%tmp2 = phi i16 [ %tmp12, %bb1 ], [ %arg2, %bb ]
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%tmp3 = icmp sgt i16 %tmp2, 7
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%tmp4 = select i1 %tmp3, i16 %tmp2, i16 7
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%tmp5 = sext i8 %tmp to i64
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%tmp6 = icmp slt i64 %arg3, %tmp5
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%tmp7 = sext i1 %tmp6 to i32
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%tmp8 = select i1 %tmp6, i8 %tmp, i8 %arg4
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store volatile i8 %tmp8, i8* %ptr1
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%tmp9 = load volatile i32, i32* %ptr2
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%tmp10 = select i1 %tmp6, i32 %tmp7, i32 %tmp9
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%tmp11 = srem i32 %x, %tmp10
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%tmp12 = trunc i32 %tmp11 to i16
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br label %bb1
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}
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; Use a particular instruction pattern in order to lower to the post-RA pseudo
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; used to lower SETB into an SBB pattern in order to make sure that kind of
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; usage of a copied EFLAGS continues to work.
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define void @PR37431(i32* %arg1, i8* %arg2, i8* %arg3, i32 %arg4, i64 %arg5) nounwind {
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; X32-LABEL: PR37431:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl (%ecx), %ecx
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; X32-NEXT: movl %ecx, %edx
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; X32-NEXT: sarl $31, %edx
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; X32-NEXT: cmpl %ecx, {{[0-9]+}}(%esp)
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; X32-NEXT: sbbl %edx, %eax
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; X32-NEXT: setb %cl
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; X32-NEXT: sbbb %dl, %dl
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: movb %dl, (%edi)
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; X32-NEXT: movzbl %cl, %ecx
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; X32-NEXT: xorl %edi, %edi
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; X32-NEXT: subl %ecx, %edi
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; X32-NEXT: cltd
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; X32-NEXT: idivl %edi
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; X32-NEXT: movb %dl, (%esi)
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; X32-NEXT: popl %esi
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; X32-NEXT: popl %edi
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; X32-NEXT: retl
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;
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; X64-LABEL: PR37431:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl %ecx, %eax
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; X64-NEXT: movq %rdx, %r9
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; X64-NEXT: movslq (%rdi), %rdx
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; X64-NEXT: cmpq %rdx, %r8
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; X64-NEXT: sbbb %cl, %cl
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; X64-NEXT: cmpq %rdx, %r8
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; X64-NEXT: movb %cl, (%rsi)
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; X64-NEXT: sbbl %ecx, %ecx
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; X64-NEXT: cltd
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; X64-NEXT: idivl %ecx
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; X64-NEXT: movb %dl, (%r9)
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; X64-NEXT: retq
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entry:
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%tmp = load i32, i32* %arg1
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%tmp1 = sext i32 %tmp to i64
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%tmp2 = icmp ugt i64 %tmp1, %arg5
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%tmp3 = zext i1 %tmp2 to i8
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%tmp4 = sub i8 0, %tmp3
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store i8 %tmp4, i8* %arg2
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%tmp5 = sext i8 %tmp4 to i32
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%tmp6 = srem i32 %arg4, %tmp5
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%tmp7 = trunc i32 %tmp6 to i8
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store i8 %tmp7, i8* %arg3
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ret void
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}
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