forked from OSchip/llvm-project
62 lines
2.8 KiB
LLVM
62 lines
2.8 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that vector sign extensions lower to shifts
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; CHECK-LABEL: sext_inreg_v16i8:
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; NO-SIMD128-NOT: i8x16
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; SIMD128-NEXT: .functype sext_inreg_v16i8 (v128) -> (v128){{$}}
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; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 7{{$}}
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; SIMD128-NEXT: i8x16.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
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; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 7{{$}}
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; SIMD128-NEXT: i8x16.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <16 x i8> @sext_inreg_v16i8(<16 x i1> %x) {
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%res = sext <16 x i1> %x to <16 x i8>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: sext_inreg_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype sext_inreg_v8i16 (v128) -> (v128){{$}}
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; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 15{{$}}
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; SIMD128-NEXT: i16x8.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
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; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 15{{$}}
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; SIMD128-NEXT: i16x8.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <8 x i16> @sext_inreg_v8i16(<8 x i1> %x) {
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%res = sext <8 x i1> %x to <8 x i16>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: sext_inreg_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128-NEXT: .functype sext_inreg_v4i32 (v128) -> (v128){{$}}
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; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 31{{$}}
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; SIMD128-NEXT: i32x4.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
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; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 31{{$}}
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; SIMD128-NEXT: i32x4.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <4 x i32> @sext_inreg_v4i32(<4 x i1> %x) {
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%res = sext <4 x i1> %x to <4 x i32>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: sext_inreg_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SDIM128-VM-NOT: i64x2
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; SIMD128-NEXT: .functype sext_inreg_v2i64 (v128) -> (v128){{$}}
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; SIMD128-NEXT: i32.const $push[[T0:[0-9]+]]=, 63{{$}}
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; SIMD128-NEXT: i64x2.shl $push[[T1:[0-9]+]]=, $0, $pop[[T0]]{{$}}
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; SIMD128-NEXT: i32.const $push[[T2:[0-9]+]]=, 63{{$}}
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; SIMD128-NEXT: i64x2.shr_s $push[[R:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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define <2 x i64> @sext_inreg_v2i64(<2 x i1> %x) {
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%res = sext <2 x i1> %x to <2 x i64>
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ret <2 x i64> %res
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}
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