forked from OSchip/llvm-project
180 lines
5.5 KiB
YAML
180 lines
5.5 KiB
YAML
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=arch13 -start-before=greedy %s -o - \
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# RUN: | FileCheck %s
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#
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# Test that regalloc manages (via regalloc hints) to avoid a LOCRMux jump
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# sequence expansion, and a SELR instuction is emitted.
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--- |
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; ModuleID = 'tc.ll'
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source_filename = "tc.ll"
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target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
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@globvar = external global i32
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declare void @fun() #0
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define void @fun1() #0 {
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bb5:
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br label %bb6
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bb6: ; preds = %bb33, %bb5
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%tmp = phi i1 [ %tmp34, %bb33 ], [ undef, %bb5 ]
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br label %bb7
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bb7: ; preds = %bb7, %bb6
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%lsr.iv1 = phi [512 x i32]* [ %0, %bb7 ], [ undef, %bb6 ]
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%tmp8 = phi i32 [ %tmp27, %bb7 ], [ -1000000, %bb6 ]
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%tmp9 = phi i64 [ %tmp28, %bb7 ], [ 0, %bb6 ]
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%lsr3 = trunc i64 %tmp9 to i32
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%lsr.iv12 = bitcast [512 x i32]* %lsr.iv1 to i32*
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%tmp11 = load i32, i32* %lsr.iv12
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%tmp12 = icmp sgt i32 %tmp11, undef
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%tmp13 = trunc i64 %tmp9 to i32
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%tmp14 = select i1 %tmp12, i32 %lsr3, i32 0
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%tmp15 = select i1 %tmp12, i32 %tmp13, i32 %tmp8
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%tmp16 = load i32, i32* undef
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%tmp17 = select i1 false, i32 undef, i32 %tmp14
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%tmp18 = select i1 false, i32 undef, i32 %tmp15
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%tmp19 = select i1 false, i32 %tmp16, i32 undef
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%tmp20 = select i1 undef, i32 undef, i32 %tmp17
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%tmp21 = select i1 undef, i32 undef, i32 %tmp18
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%tmp22 = select i1 undef, i32 undef, i32 %tmp19
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%tmp23 = or i64 %tmp9, 3
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%tmp24 = icmp sgt i32 undef, %tmp22
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%tmp25 = trunc i64 %tmp23 to i32
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%tmp26 = select i1 %tmp24, i32 %tmp25, i32 %tmp20
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%tmp27 = select i1 %tmp24, i32 %tmp25, i32 %tmp21
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%tmp28 = add nuw nsw i64 %tmp9, 4
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%tmp29 = icmp eq i64 undef, 0
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%scevgep = getelementptr [512 x i32], [512 x i32]* %lsr.iv1, i64 0, i64 4
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%0 = bitcast i32* %scevgep to [512 x i32]*
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br i1 %tmp29, label %bb30, label %bb7
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bb30: ; preds = %bb7
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%tmp32 = icmp sgt i32 %tmp27, -1000000
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br i1 %tmp32, label %bb33, label %bb35
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bb33: ; preds = %bb30
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call void @fun()
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store i32 %tmp26, i32* @globvar
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%tmp34 = icmp ugt i32 undef, 1
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br label %bb6
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bb35: ; preds = %bb30
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br i1 %tmp, label %bb37, label %bb38
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bb37: ; preds = %bb35
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unreachable
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bb38: ; preds = %bb35
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unreachable
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}
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { "target-cpu"="arch13" }
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attributes #1 = { nounwind }
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...
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# CHECK: selr
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# CHECK-NOT: risblg
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---
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name: fun1
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: grx32bit }
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- { id: 1, class: addr64bit }
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- { id: 2, class: grx32bit }
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- { id: 3, class: addr64bit }
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- { id: 4, class: gr32bit }
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- { id: 5, class: grx32bit }
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- { id: 6, class: gr64bit }
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- { id: 7, class: gr64bit }
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- { id: 8, class: grx32bit }
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- { id: 9, class: grx32bit }
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- { id: 10, class: gr64bit }
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- { id: 11, class: grx32bit }
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- { id: 12, class: gr64bit }
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- { id: 13, class: grx32bit }
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- { id: 14, class: gr32bit }
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- { id: 15, class: gr32bit }
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- { id: 16, class: grx32bit }
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- { id: 17, class: grx32bit }
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- { id: 18, class: gr32bit }
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- { id: 19, class: addr64bit }
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- { id: 20, class: grx32bit }
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- { id: 21, class: gr32bit }
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- { id: 22, class: gr64bit }
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- { id: 23, class: grx32bit }
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- { id: 24, class: grx32bit }
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- { id: 25, class: grx32bit }
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- { id: 26, class: addr64bit }
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- { id: 27, class: grx32bit }
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- { id: 28, class: addr64bit }
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frameInfo:
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hasCalls: true
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body: |
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bb.0.bb5:
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%25:grx32bit = IMPLICIT_DEF
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bb.1.bb6:
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%28:addr64bit = LGHI 0
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%27:grx32bit = IIFMux 4293967296
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%26:addr64bit = IMPLICIT_DEF
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bb.2.bb7:
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successors: %bb.3(0x04000000), %bb.2(0x7c000000)
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%14:gr32bit = LMux %26, 0, $noreg :: (load 4 from %ir.lsr.iv12)
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CR %14, undef %15:gr32bit, implicit-def $cc
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%16:grx32bit = COPY %28.subreg_l32
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%16:grx32bit = LOCHIMux %16, 0, 14, 12, implicit $cc
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%17:grx32bit = SELRMux %27, %28.subreg_l32, 14, 2, implicit killed $cc
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%18:gr32bit = LMux undef %19:addr64bit, 0, $noreg :: (load 4 from `i32* undef`)
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%20:grx32bit = COPY %28.subreg_l32
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%20:grx32bit = OILMux %20, 3, implicit-def dead $cc
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CR undef %21:gr32bit, %18, implicit-def $cc
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%4:gr32bit = SELRMux %16, %20, 14, 2, implicit $cc
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%27:grx32bit = SELRMux %17, %20, 14, 2, implicit killed $cc
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%28:addr64bit = nuw nsw LA %28, 4, $noreg
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%26:addr64bit = LA %26, 16, $noreg
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CGHI undef %22:gr64bit, 0, implicit-def $cc
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BRC 14, 6, %bb.2, implicit killed $cc
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J %bb.3
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bb.3.bb30:
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successors: %bb.4(0x7fffffff), %bb.5(0x00000001)
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CFIMux %27, -999999, implicit-def $cc
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BRC 14, 4, %bb.5, implicit killed $cc
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J %bb.4
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bb.4.bb33:
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ADJCALLSTACKDOWN 0, 0
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CallBRASL @fun, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
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ADJCALLSTACKUP 0, 0
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STRL %4, @globvar :: (store 4 into @globvar)
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CLFIMux undef %23:grx32bit, 1, implicit-def $cc
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%25:grx32bit = LHIMux 0
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%25:grx32bit = LOCHIMux %25, 1, 14, 2, implicit killed $cc
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J %bb.1
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bb.5.bb35:
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successors: %bb.6, %bb.7
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TMLMux %25, 1, implicit-def $cc
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BRC 15, 8, %bb.7, implicit killed $cc
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J %bb.6
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bb.6.bb37:
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successors:
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bb.7.bb38:
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...
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