llvm-project/llvm/test/CodeGen/MIR/X86
Guillaume Chatelet 48904e9452 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
2019-09-11 11:16:48 +00:00
..
auto-successor.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
basic-block-liveins.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
basic-block-not-at-start-of-line-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
block-address-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
branch-folder-with-label.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
branch-probabilities.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
call-site-info-error1.mir [MachineFunction] Base support for call site info tracking 2019-06-27 07:48:06 +00:00
call-site-info-error2.mir [MachineFunction] Base support for call site info tracking 2019-06-27 07:48:06 +00:00
call-site-info-error3.mir [MachineFunction] Base support for call site info tracking 2019-06-27 07:48:06 +00:00
call-site-info-error4.mir [MachineFunction] Base support for call site info tracking 2019-06-27 07:48:06 +00:00
callee-saved-info.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
cfi-def-cfa-offset.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cfi-def-cfa-register.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cfi-offset.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
constant-pool-item-redefinition-error.mir
constant-pool.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
constant-value-error.mir
copyIRflags.mir add IR flags to MI 2018-09-11 21:35:32 +00:00
dead-register-flag.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
def-register-already-tied-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
diexpr-win32.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
duplicate-memory-operand-flag.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
duplicate-register-flag-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
early-clobber-register-flag.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
empty0.mir Add triples or specify REQUIRES: default_triple to some tests 2018-01-27 23:31:09 +00:00
empty1.mir Add triples or specify REQUIRES: default_triple to some tests 2018-01-27 23:31:09 +00:00
empty2.mir Add triples or specify REQUIRES: default_triple to some tests 2018-01-27 23:31:09 +00:00
escape-function-name.ll [YAML] Add support for non-printable characters 2017-12-18 17:38:03 +00:00
expected-align-in-memory-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-alignment-after-align-in-memory-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-basic-block-at-start-of-body.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-block-reference-in-blockaddress.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-comma-after-cfi-register.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-comma-after-memory-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-different-implicit-operand.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-different-implicit-register-flag.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-function-reference-after-blockaddress.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-global-value-after-blockaddress.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-integer-after-offset-sign.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-integer-after-tied-def.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-integer-in-successor-weight.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-load-or-store-in-memory-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-machine-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-metadata-node-after-debug-location.mir [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
expected-metadata-node-after-exclaim.mir [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
expected-metadata-node-in-stack-object.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
expected-named-register-in-allocation-hint.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-named-register-in-callee-saved-register.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-named-register-in-functions-livein.mir
expected-named-register-livein.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-newline-at-end-of-list.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-number-after-bb.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
expected-offset-after-cfi-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-pointer-value-in-memory-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-positive-alignment-after-align.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-power-of-2-after-align.mir MIR: Reject non-power-of-4 alignments in MMO parsing 2019-01-30 23:09:28 +00:00
expected-register-after-cfi-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-register-after-flags.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-size-integer-after-memory-operation.mir Consistently use MemoryLocation::UnknownSize to indicate unknown access size 2018-08-20 20:37:57 +00:00
expected-size-integer-after-memory-operation2.mir Consistently use MemoryLocation::UnknownSize to indicate unknown access size 2018-08-20 20:37:57 +00:00
expected-stack-object.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
expected-subregister-after-colon.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-target-flag-name.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-tied-def-after-lparen.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-value-in-memory-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
expected-virtual-register-in-functions-livein.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
external-symbol-operands.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
fastmath.mir MachineInst support mapping SDNode fast math flags for support in Back End code generation 2018-05-03 00:07:56 +00:00
fixed-stack-di.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
fixed-stack-memory-operands.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
fixed-stack-object-redefinition-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fixed-stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
frame-info-save-restore-points.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
frame-info-stack-references.mir [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
frame-setup-instruction-flag.mir [MIR] Allow frame-setup and frame-destroy on the same instruction 2018-03-13 19:53:16 +00:00
function-liveins.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
generic-instr-type.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
global-value-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
immediate-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
implicit-register-flag.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
inline-asm-registers.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
inline-asm.mir [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. 2018-01-10 00:56:48 +00:00
instr-symbols-and-mcsymbol-operands.mir [x86/MIR] Implement support for pre- and post-instruction symbols, as 2018-08-16 23:11:05 +00:00
instructions-debug-location.mir [mir] Serialize DILocation inline when not possible to use a metadata reference 2018-12-13 14:25:27 +00:00
invalid-constant-pool-item.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
invalid-debug-location.mir MIRParser: Check that instructions only reference DILocation metadata 2018-10-01 17:50:52 +00:00
invalid-metadata-node-type.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
invalid-target-flag-name.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
invalid-tied-def-index-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
jump-table-info.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
jump-table-redefinition-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
killed-register-flag.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
large-cfi-offset-number-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
large-immediate-operand-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
large-index-number-error.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
large-offset-number-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
large-size-in-memory-operand-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lit.local.cfg
liveout-register-mask.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
machine-basic-block-operands.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
machine-instructions.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
machine-verifier.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
memory-operands.mir [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class. 2019-06-18 03:23:11 +00:00
metadata-operands.mir [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
missing-closing-quote.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
missing-comma.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
missing-implicit-operand.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
named-registers.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
newline-handling.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
null-register-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr38773.mir [DebugInfo] MCP: collect and update DBG_VALUEs encountered in local block 2019-08-14 12:20:02 +00:00
register-mask-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
register-operand-class-invalid0.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
register-operand-class-invalid1.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
register-operand-class.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
register-operands-target-flag-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
renamable-register-flag.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
roundtrip.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
simple-register-allocation-hints.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
spill-slot-fixed-stack-object-aliased.mir
spill-slot-fixed-stack-object-immutable.mir
spill-slot-fixed-stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
stack-object-debug-info.mir [MIR] Add support for debug metadata for fixed stack objects 2018-04-25 18:58:06 +00:00
stack-object-invalid-name.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
stack-object-operand-name-mismatch-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
stack-object-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
stack-object-redefinition-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
standalone-register-error.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
subreg-on-physreg.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
subregister-index-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
subregister-operands.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
successor-basic-blocks-weights.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
successor-basic-blocks.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
tied-def-operand-invalid.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
tied-physical-regs-match.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undef-register-flag.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-fixed-stack-object.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-global-value.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-ir-block-in-blockaddress.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-ir-block-slot-in-blockaddress.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-jump-table-id.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
undefined-named-global-value.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-register-class.mir
undefined-stack-object.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-value-in-memory-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
undefined-virtual-register.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unexpected-type-phys.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unknown-instruction.mir
unknown-machine-basic-block.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
unknown-metadata-keyword.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unknown-metadata-node.mir [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
unknown-named-machine-basic-block.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
unknown-register.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unknown-subregister-index-op.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unknown-subregister-index.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unreachable_block.ll [MIRPrinter] Print empty successor lists when they cannot be guessed 2017-09-19 23:34:12 +00:00
unrecognized-character.mir
variable-sized-stack-object-size-error.mir
variable-sized-stack-objects.mir Describe stack-id as an enum 2019-06-17 09:13:29 +00:00
virtual-register-redefinition-error.mir
virtual-registers.mir [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand. 2019-04-05 19:28:09 +00:00
zero-probability.mir Add 'REQUIRES: default_triple' to test/CodeGen/MIR/X86/zero-probability.mir 2018-11-07 23:33:55 +00:00