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llvm-project/llvm/test/CodeGen/MIR
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Jinsong Ji 455a0db01a [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 
All tests with -run-pass !=none should not in MIR/, See MIR/README.

```
Tests for codegen passes should NOT be here but in
test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.
```

llvm-svn: 371857
 		2019-09-13 14:18:36 +00:00
..
AArch64 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
AMDGPU [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
ARM Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
Generic [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Hexagon [DebugInfo] Allow bundled calls in the MIR's call site info 2019-08-19 12:41:22 +00:00
Mips Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
NVPTX [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. 2018-01-10 00:56:48 +00:00
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>) 2018-05-08 02:02:50 +00:00
X86 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.