llvm-project/llvm/test/CodeGen/Thumb/iabs-vector.ll

21 lines
758 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv7--- | FileCheck %s
define void @PR41160(<8 x i32>* %p) nounwind {
; CHECK-LABEL: PR41160:
; CHECK: @ %bb.0:
; CHECK-NEXT: vld1.8 {d16, d17}, [r0]
; CHECK-NEXT: vabs.s32 q8, q8
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]!
; CHECK-NEXT: vld1.8 {d16, d17}, [r0]
; CHECK-NEXT: vabs.s32 q8, q8
; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
; CHECK-NEXT: bx lr
%tmp1 = load <8 x i32>, <8 x i32>* %p, align 1
%tmp2 = icmp slt <8 x i32> %tmp1, zeroinitializer
%tmp3 = sub nsw <8 x i32> zeroinitializer, %tmp1
%tmp4 = select <8 x i1> %tmp2, <8 x i32> %tmp3, <8 x i32> %tmp1
store <8 x i32> %tmp4, <8 x i32>* %p, align 1
ret void
}