forked from OSchip/llvm-project
260 lines
6.6 KiB
LLVM
260 lines
6.6 KiB
LLVM
; RUN: llc < %s -march=sparc -mcpu=v9 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: test_atomic_i8
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; CHECK: ldub [%o0]
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; CHECK: membar
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; CHECK: ldub [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: stb {{.+}}, [%o2]
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define i8 @test_atomic_i8(i8* %ptr1, i8* %ptr2, i8* %ptr3) {
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entry:
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%0 = load atomic i8, i8* %ptr1 acquire, align 1
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%1 = load atomic i8, i8* %ptr2 acquire, align 1
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%2 = add i8 %0, %1
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store atomic i8 %2, i8* %ptr3 release, align 1
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ret i8 %2
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}
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; CHECK-LABEL: test_atomic_i16
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; CHECK: lduh [%o0]
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; CHECK: membar
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; CHECK: lduh [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: sth {{.+}}, [%o2]
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define i16 @test_atomic_i16(i16* %ptr1, i16* %ptr2, i16* %ptr3) {
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entry:
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%0 = load atomic i16, i16* %ptr1 acquire, align 2
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%1 = load atomic i16, i16* %ptr2 acquire, align 2
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%2 = add i16 %0, %1
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store atomic i16 %2, i16* %ptr3 release, align 2
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ret i16 %2
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}
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; CHECK-LABEL: test_atomic_i32
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; CHECK: ld [%o0]
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; CHECK: membar
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; CHECK: ld [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: st {{.+}}, [%o2]
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define i32 @test_atomic_i32(i32* %ptr1, i32* %ptr2, i32* %ptr3) {
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entry:
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%0 = load atomic i32, i32* %ptr1 acquire, align 4
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%1 = load atomic i32, i32* %ptr2 acquire, align 4
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%2 = add i32 %0, %1
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store atomic i32 %2, i32* %ptr3 release, align 4
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ret i32 %2
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}
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;; TODO: the "move %icc" and related instructions are totally
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;; redundant here. There's something weird happening in optimization
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;; of the success value of cmpxchg.
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; CHECK-LABEL: test_cmpxchg_i8
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; CHECK: and %o1, -4, %o2
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; CHECK: mov 3, %o3
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; CHECK: andn %o3, %o1, %o1
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; CHECK: sll %o1, 3, %o1
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; CHECK: mov 255, %o3
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; CHECK: sll %o3, %o1, %o5
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; CHECK: xor %o5, -1, %o3
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; CHECK: mov 123, %o4
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; CHECK: ld [%o2], %g2
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; CHECK: sll %o4, %o1, %o4
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; CHECK: and %o0, 255, %o0
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; CHECK: sll %o0, %o1, %o0
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; CHECK: andn %g2, %o5, %g2
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; CHECK: mov %g0, %o5
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; CHECK: [[LABEL1:\.L.*]]:
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; CHECK: or %g2, %o4, %g3
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; CHECK: or %g2, %o0, %g4
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; CHECK: cas [%o2], %g4, %g3
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; CHECK: cmp %g3, %g4
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; CHECK: mov %o5, %g4
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; CHECK: move %icc, 1, %g4
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; CHECK: cmp %g4, 0
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; CHECK: bne [[LABEL2:\.L.*]]
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; CHECK: nop
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; CHECK: and %g3, %o3, %g4
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; CHECK: cmp %g2, %g4
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; CHECK: bne [[LABEL1]]
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; CHECK: mov %g4, %g2
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; CHECK: [[LABEL2]]:
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; CHECK: retl
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; CHECK: srl %g3, %o1, %o0
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define i8 @test_cmpxchg_i8(i8 %a, i8* %ptr) {
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entry:
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%pair = cmpxchg i8* %ptr, i8 %a, i8 123 monotonic monotonic
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%b = extractvalue { i8, i1 } %pair, 0
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ret i8 %b
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}
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; CHECK-LABEL: test_cmpxchg_i16
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; CHECK: and %o1, -4, %o2
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; CHECK: and %o1, 3, %o1
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; CHECK: xor %o1, 2, %o1
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; CHECK: sll %o1, 3, %o1
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; CHECK: sethi 63, %o3
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; CHECK: or %o3, 1023, %o4
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; CHECK: sll %o4, %o1, %o5
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; CHECK: xor %o5, -1, %o3
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; CHECK: and %o0, %o4, %o4
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; CHECK: ld [%o2], %g2
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; CHECK: mov 123, %o0
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; CHECK: sll %o0, %o1, %o0
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; CHECK: sll %o4, %o1, %o4
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; CHECK: andn %g2, %o5, %g2
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; CHECK: mov %g0, %o5
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; CHECK: [[LABEL1:\.L.*]]:
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; CHECK: or %g2, %o0, %g3
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; CHECK: or %g2, %o4, %g4
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; CHECK: cas [%o2], %g4, %g3
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; CHECK: cmp %g3, %g4
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; CHECK: mov %o5, %g4
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; CHECK: move %icc, 1, %g4
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; CHECK: cmp %g4, 0
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; CHECK: bne [[LABEL2:\.L.*]]
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; CHECK: nop
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; CHECK: and %g3, %o3, %g4
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; CHECK: cmp %g2, %g4
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; CHECK: bne [[LABEL1]]
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; CHECK: mov %g4, %g2
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; CHECK: [[LABEL2]]:
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; CHECK: retl
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; CHECK: srl %g3, %o1, %o0
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define i16 @test_cmpxchg_i16(i16 %a, i16* %ptr) {
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entry:
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%pair = cmpxchg i16* %ptr, i16 %a, i16 123 monotonic monotonic
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%b = extractvalue { i16, i1 } %pair, 0
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ret i16 %b
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}
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; CHECK-LABEL: test_cmpxchg_i32
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; CHECK: mov 123, [[R:%[gilo][0-7]]]
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; CHECK: cas [%o1], %o0, [[R]]
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define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
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entry:
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%pair = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
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%b = extractvalue { i32, i1 } %pair, 0
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ret i32 %b
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}
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; CHECK-LABEL: test_swap_i8
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; CHECK: mov 42, [[R:%[gilo][0-7]]]
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; CHECK: cas
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define i8 @test_swap_i8(i8 %a, i8* %ptr) {
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entry:
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%b = atomicrmw xchg i8* %ptr, i8 42 monotonic
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ret i8 %b
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}
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; CHECK-LABEL: test_swap_i16
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; CHECK: mov 42, [[R:%[gilo][0-7]]]
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; CHECK: cas
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define i16 @test_swap_i16(i16 %a, i16* %ptr) {
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entry:
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%b = atomicrmw xchg i16* %ptr, i16 42 monotonic
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ret i16 %b
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}
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; CHECK-LABEL: test_swap_i32
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; CHECK: mov 42, [[R:%[gilo][0-7]]]
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; CHECK: swap [%o1], [[R]]
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define i32 @test_swap_i32(i32 %a, i32* %ptr) {
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entry:
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%b = atomicrmw xchg i32* %ptr, i32 42 monotonic
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ret i32 %b
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}
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; CHECK-LABEL: test_load_sub_i8
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; CHECK: membar
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; CHECK: .L{{.*}}:
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; CHECK: sub
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; CHECK: cas [{{%[gilo][0-7]}}]
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; CHECK: membar
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define zeroext i8 @test_load_sub_i8(i8* %p, i8 zeroext %v) {
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entry:
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%0 = atomicrmw sub i8* %p, i8 %v seq_cst
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ret i8 %0
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}
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; CHECK-LABEL: test_load_sub_i16
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; CHECK: membar
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; CHECK: .L{{.*}}:
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; CHECK: sub
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; CHECK: cas [{{%[gilo][0-7]}}]
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; CHECK: membar
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define zeroext i16 @test_load_sub_i16(i16* %p, i16 zeroext %v) {
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entry:
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%0 = atomicrmw sub i16* %p, i16 %v seq_cst
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ret i16 %0
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}
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; CHECK-LABEL: test_load_add_i32
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; CHECK: membar
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; CHECK: mov %g0
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; CHECK: mov [[U:%[gilo][0-7]]], [[V:%[gilo][0-7]]]
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; CHECK: add [[U:%[gilo][0-7]]], %o1, [[V2:%[gilo][0-7]]]
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; CHECK: cas [%o0], [[V]], [[V2]]
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; CHECK: membar
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define zeroext i32 @test_load_add_i32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw add i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_xor_32
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; CHECK: membar
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; CHECK: xor
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw xor i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_and_32
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; CHECK: membar
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; CHECK: and
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; CHECK-NOT: xor
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw and i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_nand_32
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; CHECK: membar
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; CHECK: and
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; CHECK: xor
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw nand i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_umin_32
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; CHECK: membar
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; CHECK: cmp
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; CHECK: movleu %icc
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw umin i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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