forked from OSchip/llvm-project
68 lines
2.1 KiB
LLVM
68 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
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; Test that we correctly align elements when using va_arg
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define i64 @test1(i32 %i, ...) nounwind optsize {
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .pad #12
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; CHECK-NEXT: sub sp, sp, #12
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, sp, #4
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: stmib sp, {r1, r2, r3}
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; CHECK-NEXT: add r0, r0, #7
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; CHECK-NEXT: bic r1, r0, #7
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; CHECK-NEXT: orr r0, r1, #4
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; CHECK-NEXT: str r0, [sp]
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; CHECK-NEXT: ldr r0, [r1]
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; CHECK-NEXT: add r2, r1, #8
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; CHECK-NEXT: str r2, [sp]
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; CHECK-NEXT: ldr r1, [r1, #4]
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; CHECK-NEXT: add sp, sp, #4
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; CHECK-NEXT: add sp, sp, #12
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; CHECK-NEXT: bx lr
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entry:
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%g = alloca i8*, align 4
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%g1 = bitcast i8** %g to i8*
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call void @llvm.va_start(i8* %g1)
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%0 = va_arg i8** %g, i64
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call void @llvm.va_end(i8* %g1)
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ret i64 %0
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}
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define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .pad #8
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; CHECK-NEXT: sub sp, sp, #8
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, sp, #4
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; CHECK-NEXT: add r0, sp, #4
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; CHECK-NEXT: stmib sp, {r2, r3}
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; CHECK-NEXT: add r0, r0, #11
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; CHECK-NEXT: bic r0, r0, #3
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; CHECK-NEXT: str r2, [r1]
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; CHECK-NEXT: add r1, r0, #8
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; CHECK-NEXT: str r1, [sp]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: add sp, sp, #4
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; CHECK-NEXT: add sp, sp, #8
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; CHECK-NEXT: bx lr
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entry:
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%ap = alloca i8*, align 4 ; <i8**> [#uses=3]
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%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]
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call void @llvm.va_start(i8* %ap1)
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%0 = va_arg i8** %ap, i32 ; <i32> [#uses=0]
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store i32 %0, i32* %b
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%1 = va_arg i8** %ap, double ; <double> [#uses=1]
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call void @llvm.va_end(i8* %ap1)
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ret double %1
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}
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declare void @llvm.va_start(i8*) nounwind
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declare void @llvm.va_end(i8*) nounwind
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