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AArch64
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[AArch64][SVE] Enable bf16 vector.insert
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2021-12-02 12:59:19 +00:00 |
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AMDGPU
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[AMDGPU] Set most sched model resource's BufferSize to one
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2021-12-01 22:31:28 -08:00 |
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ARC
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ARM
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[ARM] Teach getIntImmCostInst about the cost of saturating fp converts
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2021-12-02 07:56:27 +00:00 |
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AVR
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[asm] Remove explicit branch for modifier 'l'
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2021-11-19 09:19:53 -05:00 |
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BPF
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BPF: Workaround InstCombine trunc+icmp => mask+icmp Optimization
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2021-11-18 20:25:28 -08:00 |
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CSKY
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[CSKY] First patch to construct codegen infra and generate first add instruction
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2021-11-01 10:06:56 +08:00 |
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Generic
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[asm] Correctly handle special names in variants
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2021-11-15 15:37:09 -05:00 |
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Hexagon
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[NFC][llvm][Hexagon] Inclusive Terms remove uses of sanity in Hexagon taget
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2021-11-22 10:08:01 -05:00 |
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Inputs
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Lanai
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M68k
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MIR
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[DebugInfo][InstrRef][NFC] "Final" x86 test cleanup
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2021-11-29 22:56:09 +00:00 |
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MSP430
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Mips
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[SelectionDAG] Optimize expansion for rotates/funnel shifts
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2021-11-02 11:38:25 +00:00 |
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NVPTX
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[NVPTX] Add imm variants for surface and texture instructions
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2021-11-10 19:05:03 +03:00 |
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PowerPC
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[DAG][PowerPC] Enable initial ISD::BITCAST SimplifyDemandedBits/SimplifyMultipleUseDemandedBits big-endian handling
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2021-12-02 11:47:53 +00:00 |
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RISCV
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[RISCV] Add inline expansion for vector ftrunc/fceil/ffloor.
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2021-12-01 11:25:28 -08:00 |
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SPARC
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[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers
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2021-11-14 19:59:52 +01:00 |
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SystemZ
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[TwoAddressInstructionPass] Create register mapping for registers with multiple uses in the current MBB
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2021-11-29 19:01:59 -08:00 |
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Thumb
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[clang][ARM] PACBTI-M assembly support
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2021-11-30 09:28:18 +00:00 |
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Thumb2
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[ARM] Correct range in isLegalAddressImm
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2021-12-02 11:33:40 +00:00 |
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VE
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[VE][NFC] Use POSIX-compatible stream redirection
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2021-12-01 17:28:57 +01:00 |
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WebAssembly
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[DAG] Create fptosi.sat from clamped fptosi
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2021-11-30 15:29:14 +00:00 |
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WinCFGuard
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WinEH
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X86
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[X86][FP16] Only generate approximate rsqrt when Reciprocal is true for half type
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2021-12-02 13:52:45 +08:00 |
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XCore
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