forked from OSchip/llvm-project
133 lines
4.1 KiB
C++
133 lines
4.1 KiB
C++
//===-- LVLGen.cpp - LVL instruction generator ----------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "VE.h"
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#include "VESubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "lvl-gen"
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namespace {
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struct LVLGen : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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static char ID;
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LVLGen() : MachineFunctionPass(ID) {}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) override;
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unsigned getVL(const MachineInstr &MI);
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int getVLIndex(unsigned Opcode);
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};
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char LVLGen::ID = 0;
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} // end of anonymous namespace
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FunctionPass *llvm::createLVLGenPass() { return new LVLGen; }
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int LVLGen::getVLIndex(unsigned Opcode) {
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const MCInstrDesc &MCID = TII->get(Opcode);
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// If an instruction has VLIndex information, return it.
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if (HAS_VLINDEX(MCID.TSFlags))
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return GET_VLINDEX(MCID.TSFlags);
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return -1;
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}
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// returns a register holding a vector length. NoRegister is returned when
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// this MI does not have a vector length.
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unsigned LVLGen::getVL(const MachineInstr &MI) {
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int Index = getVLIndex(MI.getOpcode());
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if (Index >= 0)
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return MI.getOperand(Index).getReg();
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return VE::NoRegister;
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}
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bool LVLGen::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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#define RegName(no) \
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(MBB.getParent()->getSubtarget<VESubtarget>().getRegisterInfo()->getName(no))
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bool Changed = false;
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bool HasRegForVL = false;
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unsigned RegForVL;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end();) {
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MachineBasicBlock::iterator MI = I;
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unsigned Reg = getVL(*MI);
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if (Reg != VE::NoRegister) {
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LLVM_DEBUG(dbgs() << "Vector instruction found: ");
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LLVM_DEBUG(MI->dump());
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LLVM_DEBUG(dbgs() << "Vector length is " << RegName(Reg) << ". ");
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LLVM_DEBUG(dbgs() << "Current VL is "
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<< (HasRegForVL ? RegName(RegForVL) : "unknown")
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<< ". ");
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if (!HasRegForVL || RegForVL != Reg) {
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LLVM_DEBUG(dbgs() << "Generate a LVL instruction to load "
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<< RegName(Reg) << ".\n");
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BuildMI(MBB, I, MI->getDebugLoc(), TII->get(VE::LVLr)).addReg(Reg);
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HasRegForVL = true;
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RegForVL = Reg;
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Changed = true;
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} else {
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LLVM_DEBUG(dbgs() << "Reuse current VL.\n");
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}
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} else if (HasRegForVL) {
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// Old VL is overwritten, so disable HasRegForVL.
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if (MI->findRegisterDefOperandIdx(RegForVL, false, false, TRI) != -1) {
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LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
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LLVM_DEBUG(MI->dump());
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HasRegForVL = false;
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}
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}
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if (HasRegForVL) {
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// The latest VL is killed, so disable HasRegForVL.
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if (MI->killsRegister(RegForVL, TRI)) {
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LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
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LLVM_DEBUG(MI->dump());
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HasRegForVL = false;
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}
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}
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++I;
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}
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return Changed;
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}
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bool LVLGen::runOnMachineFunction(MachineFunction &F) {
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LLVM_DEBUG(dbgs() << "********** Begin LVLGen **********\n");
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LLVM_DEBUG(dbgs() << "********** Function: " << F.getName() << '\n');
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LLVM_DEBUG(F.dump());
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bool Changed = false;
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const VESubtarget &Subtarget = F.getSubtarget<VESubtarget>();
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TII = Subtarget.getInstrInfo();
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TRI = Subtarget.getRegisterInfo();
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for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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if (Changed) {
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LLVM_DEBUG(dbgs() << "\n");
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LLVM_DEBUG(F.dump());
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}
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LLVM_DEBUG(dbgs() << "********** End LVLGen **********\n");
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return Changed;
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}
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