forked from OSchip/llvm-project
111 lines
3.4 KiB
LLVM
111 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \
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; RUN: -target-abi ilp32f < %s | FileCheck %s -check-prefix=RV32IF
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \
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; RUN: -target-abi ilp32d < %s | FileCheck %s -check-prefix=RV32IFD
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \
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; RUN: -target-abi lp64d < %s | FileCheck %s -check-prefix=RV64IFD
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; Test fcopysign scenarios where the sign argument is casted to the type of the
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; magnitude argument. Those casts can be folded away by the DAGCombiner.
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declare double @llvm.copysign.f64(double, double)
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declare float @llvm.copysign.f32(float, float)
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define double @fold_promote(double %a, float %b) nounwind {
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; RV32I-LABEL: fold_promote:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a3, 524288
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; RV32I-NEXT: and a2, a2, a3
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; RV32I-NEXT: addi a3, a3, -1
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fold_promote:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a2, zero, -1
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; RV64I-NEXT: slli a2, a2, 63
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; RV64I-NEXT: addi a2, a2, -1
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: slli a2, a2, 31
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32IF-LABEL: fold_promote:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.x.w a2, fa0
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; RV32IF-NEXT: lui a3, 524288
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; RV32IF-NEXT: and a2, a2, a3
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; RV32IF-NEXT: addi a3, a3, -1
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; RV32IF-NEXT: and a1, a1, a3
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; RV32IF-NEXT: or a1, a1, a2
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; RV32IF-NEXT: ret
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;
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; RV32IFD-LABEL: fold_promote:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: fcvt.d.s ft0, fa1
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; RV32IFD-NEXT: fsgnj.d fa0, fa0, ft0
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fold_promote:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fcvt.d.s ft0, fa1
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; RV64IFD-NEXT: fsgnj.d fa0, fa0, ft0
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; RV64IFD-NEXT: ret
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%c = fpext float %b to double
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%t = call double @llvm.copysign.f64(double %a, double %c)
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ret double %t
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}
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define float @fold_demote(float %a, double %b) nounwind {
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; RV32I-LABEL: fold_demote:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: and a2, a2, a1
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: fold_demote:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a2, 524288
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; RV64I-NEXT: addiw a2, a2, -1
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; RV64I-NEXT: and a0, a0, a2
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; RV64I-NEXT: addi a2, zero, -1
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; RV64I-NEXT: slli a2, a2, 63
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: srli a1, a1, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV32IF-LABEL: fold_demote:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fsgnj.s fa0, fa0, ft0
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; RV32IF-NEXT: ret
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;
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; RV32IFD-LABEL: fold_demote:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: fcvt.s.d ft0, fa1
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; RV32IFD-NEXT: fsgnj.s fa0, fa0, ft0
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fold_demote:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fcvt.s.d ft0, fa1
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; RV64IFD-NEXT: fsgnj.s fa0, fa0, ft0
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; RV64IFD-NEXT: ret
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%c = fptrunc double %b to float
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%t = call float @llvm.copysign.f32(float %a, float %c)
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ret float %t
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}
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