llvm-project/llvm/test/CodeGen
Matt Arsenault b1dac0cfcd AMDGPU: Remove leftover test 2020-08-05 14:43:21 -04:00
..
AArch64 [SVE] Add lowering for fixed length vector and, or & xor operations. 2020-08-05 11:28:34 +01:00
AMDGPU AMDGPU: Remove leftover test 2020-08-05 14:43:21 -04:00
ARC
ARM [ARM] Generated SSAT and USAT instructions with shift 2020-08-04 09:38:17 +00:00
AVR
BPF BPF: simplify IR generation for __builtin_btf_type_id() 2020-08-04 16:29:42 -07:00
Generic [llc] (almost) remove `--print-machineinstrs` 2020-07-20 10:43:28 -07:00
Hexagon [Hexagon] Use InstSimplify instead of ConstantProp 2020-08-04 15:42:39 -07:00
Inputs
Lanai
MIR AMDGPU: Serialize MFI spill fields 2020-07-28 20:01:57 -04:00
MSP430 [MSP430] Declare comparison LibCalls as returning i16 instead of i32 2020-06-30 11:04:22 +03:00
Mips [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
NVPTX
PowerPC [PowerPC] Don't remove single swap between the load and store 2020-08-04 10:38:15 -05:00
RISCV [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SPARC [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZ] Ensure -mno-vx disables any use of vector features 2020-07-23 15:34:59 +02:00
Thumb
Thumb2 [ARM] Convert VPSEL to VMOV in tail predicated loops 2020-08-03 22:03:14 +01:00
VE [VE] Change calling convention to follow ABI 2020-08-01 10:08:54 +09:00
WebAssembly [WebAssembly] Implement prototype v128.load{32,64}_zero instructions 2020-08-03 13:54:00 -07:00
WinCFGuard
WinEH
X86 [X86][SSE] Fold 128-bit PACK(EXTEND(X),EXTEND(Y)) -> CONCAT(X,Y) subvectors 2020-08-05 18:27:40 +01:00
XCore