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llvm-project/llvm/lib/Target/AArch64
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Sander de Smalen e2c10f8f47 This is a recommit of r336322, previously reverted in r336324 due to 
a deficiency in TableGen that has been addressed in r336334.

[AArch64][SVE] Asm: Support for predicated FP rounding instructions.

This patch also adds instructions for predicated FP square-root and
reciprocal exponent.

The added instructions are:
- FRINTI  Round to integral value (current FPCR rounding mode)
- FRINTX  Round to integral value (current FPCR rounding mode, signalling inexact)
- FRINTA  Round to integral value (to nearest, with ties away from zero)
- FRINTN  Round to integral value (to nearest, with ties to even)
- FRINTZ  Round to integral value (toward zero)
- FRINTM  Round to integral value (toward minus Infinity)
- FRINTP  Round to integral value (toward plus Infinity)
- FSQRT   Floating-point square root
- FRECPX  Floating-point reciprocal exponent

llvm-svn: 336387
 		2018-07-05 20:21:21 +00:00
..
AsmParser Try to fix -Wimplicit-fallthrough warning. NFCI. 2018-07-05 09:48:01 +00:00
Disassembler [AArch64] Make function parameter names in declarations match those of definitions 2018-07-03 19:07:53 +00:00
InstPrinter Reapply r334980 and r334983. 2018-07-02 07:34:52 +00:00
MCTargetDesc [AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions. 2018-06-15 15:47:44 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
Utils [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates. 2018-06-15 13:11:49 +00:00
AArch64.h Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64 2018-05-09 05:00:17 +00:00
AArch64.td [ARM][AArch64] Armv8.4-A Enablement 2018-06-29 08:43:19 +00:00
AArch64A53Fix835769.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64A57FPLoadBalancing.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64AdvSIMDScalarPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64AsmPrinter.cpp [AArch64] Support "S" inline assembler constraint 2018-05-16 09:33:25 +00:00
AArch64CallLowering.cpp [AArch64][GlobalISel] Fix fallbacks introduced in r336120 due to unselectable stores. 2018-07-03 15:59:26 +00:00
AArch64CallLowering.h GlobalISel (AArch64): fix ABI at border between GPRs and SP. 2017-08-21 21:56:11 +00:00
AArch64CallingConvention.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64CallingConvention.td AArch64: Implement support for the shadowcallstack attribute. 2018-04-04 21:55:44 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64CondBrTuning.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionOptimizer.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionalCompares.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64DeadRegisterDefinitionsPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Improve orr+movk sequences for MOVi64imm. 2018-05-24 19:38:23 +00:00
AArch64FalkorHWPFFix.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64FastISel.cpp Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AArch64FrameLowering.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64FrameLowering.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AArch64GenRegisterBankInfo.def [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies 2017-11-18 04:28:56 +00:00
AArch64ISelDAGToDAG.cpp Revert "[AArch64] Coalesce Copy Zero during instruction selection" 2018-06-21 16:05:24 +00:00
AArch64ISelLowering.cpp [AArch64] Add custom lowering for v4i8 trunc store 2018-06-27 13:58:46 +00:00
AArch64ISelLowering.h [AArch64] Add custom lowering for v4i8 trunc store 2018-06-27 13:58:46 +00:00
AArch64InstrAtomics.td [AArch64] Improve v8.1-A code-gen for atomic load-and 2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td [AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD 2018-07-05 07:54:10 +00:00
AArch64InstrInfo.cpp [MachineOutliner] Fix typo in getOutliningCandidateInfo function name 2018-07-04 15:37:08 +00:00
AArch64InstrInfo.h [MachineOutliner] Fix typo in getOutliningCandidateInfo function name 2018-07-04 15:37:08 +00:00
AArch64InstrInfo.td [AArch64] Reverting FP16 vcvth_n_s64_f16 to fix 2018-06-27 14:34:40 +00:00
AArch64InstructionSelector.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64LegalizerInfo.cpp [globalisel][legalizer] Add AtomicOrdering to LegalityQuery and use it in AArch64 2018-06-27 19:03:21 +00:00
AArch64LegalizerInfo.h [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal 2017-11-28 20:21:15 +00:00
AArch64LoadStoreOptimizer.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64MCInstLower.cpp Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
AArch64MCInstLower.h
…
AArch64MachineFunctionInfo.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AArch64MacroFusion.cpp Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AArch64MacroFusion.h
…
AArch64PBQPRegAlloc.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PromoteConstant.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64RedundantCopyElimination.cpp [CodeGen][AArch64] Use RegUnits to track register aliases. (NFC) 2018-05-23 17:49:38 +00:00
AArch64RegisterBankInfo.cpp [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h [AArch64][RegisterBankInfo] Add mapping for G_FPEXT. 2017-11-02 23:38:19 +00:00
AArch64RegisterBanks.td [aarch64][globalisel] Register banks and classes should have distinct names. 2017-10-18 00:12:43 +00:00
AArch64RegisterInfo.cpp [AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existing patterns 2018-06-27 09:20:13 +00:00
AArch64RegisterInfo.h [AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existing patterns 2018-06-27 09:20:13 +00:00
AArch64RegisterInfo.td [AArch64][SVE] Asm: Support for FMUL (indexed) 2018-07-03 15:31:04 +00:00
AArch64SIMDInstrOpt.cpp [TargetSchedule] shrink interface for init(); NFCI 2018-04-08 19:56:04 +00:00
AArch64SVEInstrInfo.td This is a recommit of r336322, previously reverted in r336324 due to 2018-07-05 20:21:21 +00:00
AArch64SchedA53.td [AArch64] Clean-up a few over-eager regexps in models. 2018-03-23 11:00:42 +00:00
AArch64SchedA57.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedExynosM1.td [ExynosM1][Sched] Fix resource usage in scheduling model. 2018-06-11 07:33:08 +00:00
AArch64SchedExynosM3.td [ExynosM3] Fix scheduling info. 2018-05-18 13:10:41 +00:00
AArch64SchedFalkor.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Correct load/store increment scheduling details 2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
…
AArch64SchedThunderX.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedThunderX2T99.td [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles. 2018-06-13 09:41:49 +00:00
AArch64Schedule.td
…
AArch64SelectionDAGInfo.cpp AArch64/X86: Factor out common bzero logic; NFC 2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
…
AArch64StorePairSuppress.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64Subtarget.cpp AArch64: Implement support for the shadowcallstack attribute. 2018-04-04 21:55:44 +00:00
AArch64Subtarget.h [ARM][AArch64] Armv8.4-A Enablement 2018-06-29 08:43:19 +00:00
AArch64SystemOperands.td [AArch64] Armv8.4-A: system registers 2018-07-03 12:09:20 +00:00
AArch64TargetMachine.cpp [MachineOutliner] Define MachineOutliner support in TargetOptions 2018-06-28 17:45:43 +00:00
AArch64TargetMachine.h (Re-landing) Expose a TargetMachine::getTargetTransformInfo function 2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp
…
AArch64TargetObjectFile.h Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp [AArch64] Add custom lowering for v4i8 trunc store 2018-06-27 13:58:46 +00:00
AArch64TargetTransformInfo.h [TTI, AArch64] Add transpose shuffle kind 2018-04-26 13:48:33 +00:00
CMakeLists.txt Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64 2018-05-09 05:00:17 +00:00
LLVMBuild.txt
…
SVEInstrFormats.td This is a recommit of r336322, previously reverted in r336324 due to 2018-07-05 20:21:21 +00:00