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llvm-project/mlir/test/Dialect
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Aart Bik 0e85232fa3 [mlir][sparse] refine simply dynamic sparse tensor outputs 
Proper test for sparse tensor outputs is a single condition throughout
the whole tensor index expression (not a general conjunction, since this
may include other conditions that cause cancellation).

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D114810
 		2021-11-30 13:45:58 -08:00
..
AMX [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
Affine [MLIR] Simplify Semi-affine expressions by rule based matching and replacing "expr - q * (expr floordiv q)" with "expr mod q" expression. 2021-11-20 21:05:36 +05:30
Arithmetic [mlir] Move memref.[tensor_load|buffer_cast|clone] to "bufferization" dialect. 2021-11-25 11:50:39 +01:00
ArmNeon 2d Arm Neon sdot op, and lowering to the intrinsic. 2021-06-10 14:36:39 -07:00
ArmSVE [mlir:DialectConversion] Restructure how argument/target materializations get invoked 2021-10-27 02:09:04 +00:00
Async [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
Bufferization [mlir] Move bufferization-related passes to `bufferization` dialect. 2021-11-30 09:58:47 +01:00
Builtin Add a new interface allowing to set a default dialect to be used for printing/parsing regions 2021-08-31 17:52:40 +00:00
Complex [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
DLTI [mlir] support data layout specs on ModuleOp 2021-03-24 15:13:38 +01:00
EmitC [mlir] Fix printing of EmitC attrs/types with escape characters 2021-09-15 18:15:38 +00:00
GPU [mlir][gpu] Extend shuffle op modes and add nvvm lowering 2021-11-19 11:14:31 -08:00
LLVMIR [mlir][gpu] Extend shuffle op modes and add nvvm lowering 2021-11-19 11:14:31 -08:00
Linalg [mlir][tensor] InsertSliceOp verification. 2021-11-30 20:37:06 +00:00
Math [mlir] MathApproximations: unroll virtual vectors into hardware vectors for ISA specific operation 2021-10-28 12:52:04 -07:00
MemRef [mlir][tensor] InsertSliceOp verification. 2021-11-30 20:37:06 +00:00
OpenACC [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
OpenMP [mlir][OpenMP] Add support for SIMD modifier 2021-11-26 14:04:46 +00:00
PDL Multi-root PDL matching using upward traversals. 2021-11-26 18:11:37 +05:30
PDLInterp Defines new PDLInterp operations needed for multi-root matching in PDL. 2021-11-26 17:59:22 +05:30
Quant [MLIR] Replace std ops with arith dialect ops 2021-10-13 03:07:03 +00:00
SCF [mlir][tensor] InsertSliceOp verification. 2021-11-30 20:37:06 +00:00
SPIRV [mlir] Move trait to InferTypeOpInterface 2021-11-21 14:41:12 -08:00
Shape [mlir] Move memref.[tensor_load|buffer_cast|clone] to "bufferization" dialect. 2021-11-25 11:50:39 +01:00
SparseTensor [mlir][sparse] refine simply dynamic sparse tensor outputs 2021-11-30 13:45:58 -08:00
Standard [mlir] Move memref.[tensor_load|buffer_cast|clone] to "bufferization" dialect. 2021-11-25 11:50:39 +01:00
Tensor [mlir][tensor] InsertSliceOp verification. 2021-11-30 20:37:06 +00:00
Tosa [mlir][tosa] Add tosa.conv2d as fully_connected canonicalization 2021-11-30 12:01:14 -08:00
Vector [mlir][Vector] Thread 0-d vectors through InsertElementOp. 2021-11-23 12:55:11 +00:00
X86Vector [mlir][vector][avx] add AVX dot product to X86Vector dialect with lowering 2021-04-15 15:01:39 -07:00
traits.mlir [mlir] Fix broadcasting check with 1 values 2021-07-11 20:41:33 -07:00