llvm-project/llvm/test/Transforms/SLPVectorizer
Sanjay Patel d27a21874b [x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433)
This should fix:
https://llvm.org/bugs/show_bug.cgi?id=30433

There are a couple of open questions about the codegen:
1. Should we let scalar ops be scalars and avoid vector constant loads/splats?
2. Should we have a pass to combine constants such as the inverted pair that we have here?

Differential Revision: https://reviews.llvm.org/D25165
 

llvm-svn: 283119
2016-10-03 16:38:27 +00:00
..
AArch64 [SLP] Avoid signed integer overflow 2016-08-23 20:48:50 +00:00
AMDGPU [SLPVectorizer] Try different vectorization factors for store chains 2015-07-08 23:40:55 +00:00
ARM
PowerPC [SLP] Pass in correct alignment when query memory access cost 2016-05-31 20:41:19 +00:00
X86 [x86, SSE/AVX] allow 128/256-bit lowering for copysign vector intrinsics (PR30433) 2016-10-03 16:38:27 +00:00
XCore