forked from OSchip/llvm-project
9ca6fc4e09
The altera kernel name restriction check finds kernel files and include
directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl".
Such kernel file names cause the Altera Offline Compiler to generate
intermediate design files that have the same names as certain internal
files, which leads to a compilation error.
As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA
SDK for OpenCL Pro Edition: Programming Guide."
This reverts the reversion from
|
||
|---|---|---|
| .. | ||
| Unit | ||
| clang-apply-replacements | ||
| clang-change-namespace | ||
| clang-doc | ||
| clang-include-fixer | ||
| clang-move | ||
| clang-query | ||
| clang-reorder-fields | ||
| clang-tidy | ||
| modularize | ||
| pp-trace | ||
| .clang-format | ||
| CMakeLists.txt | ||
| lit.cfg.py | ||
| lit.site.cfg.py.in | ||