forked from OSchip/llvm-project
241 lines
8.1 KiB
TableGen
241 lines
8.1 KiB
TableGen
//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Intel Silvermont to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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def SLMModel : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and SLM can decode 2
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// instructions per cycle.
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let IssueWidth = 2;
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let MicroOpBufferSize = 32; // Based on the reorder buffer.
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let LoadLatency = 3;
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let MispredictPenalty = 10;
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let PostRAScheduler = 1;
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// For small loops, expand by a small factor to hide the backedge cost.
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let LoopMicroOpBufferSize = 10;
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// FIXME: SSE4 is unimplemented. This flag is set to allow
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// the scheduler to assign a default model to unrecognized opcodes.
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let CompleteModel = 0;
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}
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let SchedModel = SLMModel in {
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// Silvermont has 5 reservation stations for micro-ops
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def IEC_RSV0 : ProcResource<1>;
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def IEC_RSV1 : ProcResource<1>;
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def FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
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def FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
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def MEC_RSV : ProcResource<1>;
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// Many micro-ops are capable of issuing on multiple ports.
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def IEC_RSV01 : ProcResGroup<[IEC_RSV0, IEC_RSV1]>;
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def FPC_RSV01 : ProcResGroup<[FPC_RSV0, FPC_RSV1]>;
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def SMDivider : ProcResource<1>;
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def SMFPMultiplier : ProcResource<1>;
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def SMFPDivider : ProcResource<1>;
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// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 3>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when queued in the reservation station.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass SMWriteResPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [1], int UOps = 1> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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// Memory variant also uses a cycle on MEC_RSV and adds 3 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, !listconcat([MEC_RSV], ExePorts)> {
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let Latency = !add(Lat, 3);
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let ResourceCycles = !listconcat([1], Res);
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let NumMicroOps = UOps;
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}
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}
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// A folded store needs a cycle on MEC_RSV for the store data, but it does not
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// need an extra port cycle to recompute the address.
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def : WriteRes<WriteRMW, [MEC_RSV]>;
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def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>;
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def : WriteRes<WriteLoad, [MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteMove, [IEC_RSV01]>;
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def : WriteRes<WriteZero, []>;
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// Treat misc copies as a move.
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def : InstRW<[WriteMove], (instrs COPY)>;
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defm : SMWriteResPair<WriteALU, [IEC_RSV01], 1>;
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defm : SMWriteResPair<WriteIMul, [IEC_RSV1], 3>;
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defm : SMWriteResPair<WriteShift, [IEC_RSV0], 1>;
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defm : SMWriteResPair<WriteJump, [IEC_RSV1], 1>;
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// This is for simple LEAs with one or two input operands.
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// The complex ones can only execute on port 1, and they require two cycles on
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// the port to read all inputs. We don't model that.
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def : WriteRes<WriteLEA, [IEC_RSV1]>;
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// This is quite rough, latency depends on the dividend.
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def : WriteRes<WriteIDiv, [IEC_RSV01, SMDivider]> {
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let Latency = 25;
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let ResourceCycles = [1, 25];
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}
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def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> {
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let Latency = 29;
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let ResourceCycles = [1, 1, 25];
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}
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// Scalar and vector floating point.
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def : WriteRes<WriteFStore, [FPC_RSV01, MEC_RSV]>;
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def : WriteRes<WriteFLoad, [MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteFMove, [FPC_RSV01]>;
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defm : SMWriteResPair<WriteFAdd, [FPC_RSV1], 3>;
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defm : SMWriteResPair<WriteFMul, [FPC_RSV0, SMFPMultiplier], 5, [1,2]>;
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defm : SMWriteResPair<WriteFDiv, [FPC_RSV0, SMFPDivider], 34, [1,34]>;
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defm : SMWriteResPair<WriteFRcp, [FPC_RSV0], 5>;
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defm : SMWriteResPair<WriteFRsqrt, [FPC_RSV0], 5>;
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defm : SMWriteResPair<WriteFSqrt, [FPC_RSV0], 15>;
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defm : SMWriteResPair<WriteCvtF2I, [FPC_RSV01], 4>;
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defm : SMWriteResPair<WriteCvtI2F, [FPC_RSV01], 4>;
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defm : SMWriteResPair<WriteCvtF2F, [FPC_RSV01], 4>;
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defm : SMWriteResPair<WriteFShuffle, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteFBlend, [FPC_RSV0], 1>;
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// Vector integer operations.
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def : WriteRes<WriteVecStore, [FPC_RSV01, MEC_RSV]>;
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def : WriteRes<WriteVecLoad, [MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecMove, [FPC_RSV01]>;
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defm : SMWriteResPair<WriteVecShift, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteVecLogic, [FPC_RSV01], 1>;
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defm : SMWriteResPair<WriteVecALU, [FPC_RSV01], 1>;
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defm : SMWriteResPair<WriteVecIMul, [FPC_RSV0], 4>;
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defm : SMWriteResPair<WriteShuffle, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteBlend, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteMPSAD, [FPC_RSV0], 7>;
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////////////////////////////////////////////////////////////////////////////////
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// Horizontal add/sub instructions.
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////////////////////////////////////////////////////////////////////////////////
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defm : SMWriteResPair<WriteFHAdd, [FPC_RSV01], 3, [2]>;
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defm : SMWriteResPair<WritePHAdd, [FPC_RSV01], 1>;
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// String instructions.
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// Packed Compare Implicit Length Strings, Return Mask
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def : WriteRes<WritePCmpIStrM, [FPC_RSV0]> {
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let Latency = 13;
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let ResourceCycles = [13];
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}
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def : WriteRes<WritePCmpIStrMLd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 13;
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let ResourceCycles = [13, 1];
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}
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// Packed Compare Explicit Length Strings, Return Mask
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def : WriteRes<WritePCmpEStrM, [FPC_RSV0]> {
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let Latency = 17;
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let ResourceCycles = [17];
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}
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def : WriteRes<WritePCmpEStrMLd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 17;
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let ResourceCycles = [17, 1];
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}
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// Packed Compare Implicit Length Strings, Return Index
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def : WriteRes<WritePCmpIStrI, [FPC_RSV0]> {
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let Latency = 17;
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let ResourceCycles = [17];
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}
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def : WriteRes<WritePCmpIStrILd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 17;
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let ResourceCycles = [17, 1];
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}
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// Packed Compare Explicit Length Strings, Return Index
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def : WriteRes<WritePCmpEStrI, [FPC_RSV0]> {
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let Latency = 21;
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let ResourceCycles = [21];
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}
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def : WriteRes<WritePCmpEStrILd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 21;
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let ResourceCycles = [21, 1];
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}
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// AES Instructions.
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def : WriteRes<WriteAESDecEnc, [FPC_RSV0]> {
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let Latency = 8;
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let ResourceCycles = [5];
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}
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def : WriteRes<WriteAESDecEncLd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 8;
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let ResourceCycles = [5, 1];
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}
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def : WriteRes<WriteAESIMC, [FPC_RSV0]> {
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let Latency = 8;
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let ResourceCycles = [5];
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}
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def : WriteRes<WriteAESIMCLd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 8;
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let ResourceCycles = [5, 1];
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}
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def : WriteRes<WriteAESKeyGen, [FPC_RSV0]> {
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let Latency = 8;
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let ResourceCycles = [5];
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}
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def : WriteRes<WriteAESKeyGenLd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 8;
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let ResourceCycles = [5, 1];
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}
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// Carry-less multiplication instructions.
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def : WriteRes<WriteCLMul, [FPC_RSV0]> {
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let Latency = 10;
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let ResourceCycles = [10];
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}
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def : WriteRes<WriteCLMulLd, [FPC_RSV0, MEC_RSV]> {
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let Latency = 10;
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let ResourceCycles = [10, 1];
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}
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def : WriteRes<WriteSystem, [FPC_RSV0]> { let Latency = 100; }
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def : WriteRes<WriteMicrocoded, [FPC_RSV0]> { let Latency = 100; }
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def : WriteRes<WriteFence, [MEC_RSV]>;
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def : WriteRes<WriteNop, []>;
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// AVX/FMA is not supported on that architecture, but we should define the basic
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// scheduling resources anyway.
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def : WriteRes<WriteIMulH, [FPC_RSV0]>;
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defm : SMWriteResPair<WriteVarBlend, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteFVarBlend, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteFShuffle256, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteShuffle256, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteVarVecShift, [FPC_RSV0], 1>;
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defm : SMWriteResPair<WriteFMA, [FPC_RSV0], 1>;
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} // SchedModel
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