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llvm-project/llvm/test/CodeGen/RISCV
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Luis Marques 20d2424016 [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS 
When not optimizing for minimum size (-Oz) we custom lower wide shifts
(SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall.

Differential Revision: https://reviews.llvm.org/D59477

llvm-svn: 358498
 		2019-04-16 14:38:32 +00:00
..
addc-adde-sube-subc.ll
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align.ll
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alloca.ll
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alu8.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
alu16.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
alu32.ll [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions 2019-01-12 07:32:31 +00:00
alu64.ll [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS 2019-04-16 14:38:32 +00:00
analyze-branch.ll
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arith-with-overflow.ll [RISCV] Add tests for overflow intrinsics 2018-06-19 06:45:47 +00:00
atomic-cmpxchg-flag.ll [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A 2019-03-11 21:41:22 +00:00
atomic-cmpxchg.ll Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
atomic-fence.ll [RISCV][NFC] Add CHECK lines for atomic operations on RV64I 2019-01-11 19:46:48 +00:00
atomic-load-store.ll [RISCV] Add codegen support for RV64A 2019-01-17 10:04:39 +00:00
atomic-rmw.ll [RISCV] Optimize emission of SELECT sequences 2019-03-22 10:45:03 +00:00
bare-select.ll
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blockaddress.ll
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branch-relaxation.ll
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branch.ll
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bswap-ctlz-cttz-ctpop.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
byval.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
callee-saved-fpr32s.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
callee-saved-fpr64s.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
callee-saved-gprs.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
calling-conv-ilp32d.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
calling-conv-rv32f-ilp32.ll Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
calling-conv-sext-zext.ll
…
calls.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
codemodel-lowering.ll [RISCV] Implement adding a displacement to a BlockAddress 2019-04-05 08:40:57 +00:00
compress-inline-asm.ll
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compress.ll
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disable-tail-calls.ll [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
div.ll [RISCV] Introduce codegen patterns for RV64M-only instructions 2019-01-12 07:43:06 +00:00
double-arith.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
double-bitmanip-dagcombines.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
double-br-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-calling-conv.ll [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) 2019-03-30 09:15:47 +00:00
double-convert.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
double-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-frem.ll [RISCV] Mark FREM as Expand 2018-11-15 14:46:11 +00:00
double-imm.ll [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) 2019-03-30 09:15:47 +00:00
double-intrinsics.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
double-mem.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
double-previous-failure.ll [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) 2019-03-30 09:15:47 +00:00
double-select-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-stack-spill-restore.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
fixups-diff.ll [RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true 2018-08-16 11:26:37 +00:00
fixups-relax-diff.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
float-arith.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-bitmanip-dagcombines.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-br-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
float-convert.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
float-frem.ll [RISCV] Mark FREM as Expand 2018-11-15 14:46:11 +00:00
float-imm.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-intrinsics.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
float-mem.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
float-select-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
flt-rounds.ll [SelectionDAG] Support result type promotion for FLT_ROUNDS_ 2018-11-30 13:18:33 +00:00
fp128.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
frame.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
frameaddr-returnaddr.ll [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands 2018-11-30 10:02:06 +00:00
get-setcc-result-type.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
hoist-global-addr-base.ll [RISCV] Add machine function pass to merge base + offset 2018-06-27 20:51:42 +00:00
i32-icmp.ll [RISCV] Improve codegen for icmp {ne,eq} with a constant 2019-03-26 12:55:00 +00:00
imm-cse.ll
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imm.ll Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
indirectbr.ll [RISC-V] Fix a test case to not include label names as those aren't 2018-06-21 05:42:05 +00:00
init-array.ll
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inline-asm.ll [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test 2019-02-14 13:09:54 +00:00
interrupt-attr-args-error.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-invalid.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-nocall.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-ret-error.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
jumptable.ll Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
large-stack.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
legalize-fneg.ll [RISCV] Regenerate test/CodeGen/RISCV/legalize-fneg.ll after rL356068 2019-03-13 18:25:23 +00:00
lit.local.cfg
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lsr-legaladdimm.ll
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mattr-invalid-combination.ll [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
mem.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
mem64.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
mul.ll [RISCV] Introduce codegen patterns for RV64M-only instructions 2019-01-12 07:43:06 +00:00
musttail-call.ll [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
option-norelax.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
option-norvc.ll
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option-relax.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
option-rvc.ll
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pr40333.ll [RISCV] Custom-legalise 32-bit variable shifts on RV64 2019-01-25 05:04:00 +00:00
prefetch.ll [SelectionDAG] Support promotion of PREFETCH operands 2018-11-30 10:06:31 +00:00
rem.ll [RISCV] Introduce codegen patterns for RV64M-only instructions 2019-01-12 07:43:06 +00:00
remat.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
rotl-rotr.ll
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rv32e.ll [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
rv32i-rv64i-float-double.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
rv64d-double-convert.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
rv64f-float-convert.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
rv64i-exhaustive-w-insts.ll [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions 2019-01-12 07:32:31 +00:00
rv64i-tricky-shifts.ll [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases 2018-12-01 05:00:00 +00:00
rv64m-exhaustive-w-insts.ll [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M 2019-01-25 05:11:34 +00:00
sdata-limit-0.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-4.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-8.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-local-sym.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
select-cc.ll
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select-optimize-multiple.ll [RISCV] Optimize emission of SELECT sequences 2019-03-22 10:45:03 +00:00
select-optimize-multiple.mir [RISCV] Optimize emission of SELECT sequences 2019-03-22 10:45:03 +00:00
setcc-logic.ll [RISCV] Update setcc-logic.ll codegen test 2019-03-26 15:41:45 +00:00
sext-zext-trunc.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
shift-masked-shamt.ll [RISCV] Eliminate unnecessary masking of promoted shift amounts 2018-10-12 23:18:52 +00:00
shifts.ll [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS 2019-04-16 14:38:32 +00:00
tail-calls.ll [RISCV] Fixed test case failure due to r338047 2018-07-31 00:36:28 +00:00
target-abi-invalid.ll [RISCV] Support -target-abi at the MC layer and for codegen 2019-03-09 09:28:06 +00:00
target-abi-valid.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
umulo-128-legalisation-lowering.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
vararg.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
wide-mem.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
zext-with-load-is-free.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00