forked from OSchip/llvm-project
91 lines
3.5 KiB
LLVM
91 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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; Check that building a vector from floats doesn't insert an unnecessary
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; copy for lane zero.
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define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
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; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
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; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
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; CHECK-NEXT: mov.s v0[1], v1[0]
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; CHECK-NEXT: mov.s v0[2], v2[0]
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; CHECK-NEXT: mov.s v0[3], v3[0]
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; CHECK-NEXT: ret
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%1 = insertelement <4 x float> undef, float %a, i32 0
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%2 = insertelement <4 x float> %1, float %b, i32 1
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%3 = insertelement <4 x float> %2, float %c, i32 2
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%4 = insertelement <4 x float> %3, float %d, i32 3
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ret <4 x float> %4
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}
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define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
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; CHECK-LABEL: build_all_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #44672
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: mul.8h v0, v0, v1
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; CHECK-NEXT: ret
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%b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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%c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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ret <8 x i16> %c
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}
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; There is an optimization in DAG Combiner as following:
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; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
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; -> (BUILD_VECTOR A, B, ..., C, D, ...)
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; This case checks when A,B and C,D are different types, there should be no
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; assertion failure.
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define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) {
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; CHECK-LABEL: concat_2_build_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi.2d v0, #0000000000000000
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; CHECK-NEXT: ret
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%vshl_n = shl <4 x i16> %in0, <i16 8, i16 8, i16 8, i16 8>
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%vshl_n2 = shl <4 x i16> %vshl_n, <i16 9, i16 9, i16 9, i16 9>
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%shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i
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}
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; The lowering of a widened f16 BUILD_VECTOR tries to optimize it by building
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; an equivalent integer vector and BITCAST-ing that. This case checks that
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; normalizing the vector generates a valid result. The choice of the
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; constant prevents earlier passes from replacing the BUILD_VECTOR.
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define void @widen_f16_build_vector(half* %addr) {
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; CHECK-LABEL: widen_f16_build_vector:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #13294
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; CHECK-NEXT: dup.4h v0, w8
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; CHECK-NEXT: str s0, [x0]
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; CHECK-NEXT: ret
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%1 = bitcast half* %addr to <2 x half>*
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store <2 x half> <half 0xH33EE, half 0xH33EE>, <2 x half>* %1, align 2
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ret void
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}
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; Check that a single element vector is constructed with a mov
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define <1 x i64> @single_element_vector_i64(<1 x i64> %arg) {
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; CHECK-LABEL: single_element_vector_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: add d0, d0, d1
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; CHECK-NEXT: ret
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entry:
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%add = add <1 x i64> %arg, <i64 1>
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ret <1 x i64> %add
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}
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define <1 x double> @single_element_vector_double(<1 x double> %arg) {
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; CHECK-LABEL: single_element_vector_double:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov d1, #1.00000000
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; CHECK-NEXT: fadd d0, d0, d1
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; CHECK-NEXT: ret
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entry:
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%add = fadd <1 x double> %arg, <double 1.0>
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ret <1 x double> %add
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}
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