forked from OSchip/llvm-project
144 lines
3.7 KiB
LLVM
144 lines
3.7 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -march=ppc64 -mcpu=a2q | FileCheck %s
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target triple = "powerpc64-bgq-linux"
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@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone {
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entry:
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%r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b
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ret <4 x float> %r
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; CHECK-LABEL: @test1
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; CHECK: qvfsel 1, 3, 1, 2
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; CHECK: blr
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}
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone {
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entry:
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%v = insertelement <4 x i1> undef, i1 %c1, i32 0
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%v2 = insertelement <4 x i1> %v, i1 %c2, i32 1
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%v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2
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%v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3
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%r = select <4 x i1> %v4, <4 x float> %a, <4 x float> %b
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ret <4 x float> %r
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; CHECK-LABEL: @test2
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; CHECK: stw
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; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
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; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
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; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
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; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
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; CHECK: qvfsel 1, [[REG4]], 1, 2
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; CHECK: blr
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}
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define <4 x i1> @test3(<4 x i1> %a) nounwind readnone {
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entry:
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%v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1>
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ret <4 x i1> %v
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; CHECK-LABEL: @test3
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; CHECK: qvlfsx [[REG:[0-9]+]],
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; qvflogical 1, 1, [[REG]], 1
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; blr
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}
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define <4 x i1> @test4(<4 x i1> %a, <4 x i1>* %t) nounwind {
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entry:
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%q = load <4 x i1>, <4 x i1>* %t, align 16
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%v = and <4 x i1> %a, %q
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ret <4 x i1> %v
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; CHECK-LABEL: @test4
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; CHECK-DAG: lbz
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; CHECK-DAG: qvlfdx [[REG1:[0-9]+]],
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; CHECK-DAG: stw
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; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
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; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
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; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
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; CHECK: qvflogical 1, 1, [[REG4]], 1
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; CHECK: blr
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}
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define void @test5(<4 x i1> %a) nounwind {
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entry:
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store <4 x i1> %a, <4 x i1>* @R
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ret void
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; CHECK-LABEL: @test5
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; CHECK: qvlfdx [[REG1:[0-9]+]],
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; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
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; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
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; CHECK: qvstfiwx [[REG3]],
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; CHECK: lwz
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; CHECK: stb
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; CHECK: blr
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}
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define i1 @test6(<4 x i1> %a) nounwind {
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entry:
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%r = extractelement <4 x i1> %a, i32 2
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ret i1 %r
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; CHECK-LABEL: @test6
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; CHECK: qvlfdx [[REG1:[0-9]+]],
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; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
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; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
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; CHECK: qvstfiwx [[REG3]],
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; CHECK: lwz
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; CHECK: blr
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}
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define i1 @test7(<4 x i1> %a) nounwind {
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entry:
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%r = extractelement <4 x i1> %a, i32 2
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%s = extractelement <4 x i1> %a, i32 3
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%q = and i1 %r, %s
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ret i1 %q
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; CHECK-LABEL: @test7
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; CHECK: qvlfdx [[REG1:[0-9]+]],
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; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
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; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
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; CHECK: qvstfiwx [[REG3]],
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; CHECK-DAG: lwz [[REG4:[0-9]+]],
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; FIXME: We're storing the vector twice, and that's silly.
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; CHECK-DAG: qvstfiwx [[REG3]],
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; CHECK: lwz [[REG5:[0-9]+]],
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; CHECK: and 3,
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; CHECK: blr
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}
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define i1 @test8(<3 x i1> %a) nounwind {
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entry:
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%r = extractelement <3 x i1> %a, i32 2
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ret i1 %r
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; CHECK-LABEL: @test8
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; CHECK: qvlfdx [[REG1:[0-9]+]],
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; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]]
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; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]]
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; CHECK: qvstfiwx [[REG3]],
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; CHECK: lwz
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; CHECK: blr
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}
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define <3 x float> @test9(<3 x float> %a, <3 x float> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone {
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entry:
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%v = insertelement <3 x i1> undef, i1 %c1, i32 0
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%v2 = insertelement <3 x i1> %v, i1 %c2, i32 1
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%v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2
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%r = select <3 x i1> %v3, <3 x float> %a, <3 x float> %b
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ret <3 x float> %r
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; CHECK-LABEL: @test9
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; CHECK: stw
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; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]],
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; CHECK-DAG: qvlfdx [[REG2:[0-9]+]],
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; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]]
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; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]]
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; CHECK: qvfsel 1, [[REG4]], 1, 2
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; CHECK: blr
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}
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