llvm-project/llvm/lib/Target/XCore
Zi Xuan Wu 9802268ad3 recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize
In loop-vectorize, interleave count and vector factor depend on target register number. Currently, it does not
estimate different register pressure for different register class separately(especially for scalar type,
float type should not be on the same position with int type), so it's not accurate. Specifically,
it causes too many times interleaving/unrolling, result in too many register spills in loop body and hurting performance.

So we need classify the register classes in IR level, and importantly these are abstract register classes,
and are not the target register class of backend provided in td file. It's used to establish the mapping between
the types of IR values and the number of simultaneous live ranges to which we'd like to limit for some set of those types.

For example, POWER target, register num is special when VSX is enabled. When VSX is enabled, the number of int scalar register is 32(GPR),
float is 64(VSR), but for int and float vector register both are 64(VSR). So there should be 2 kinds of register class when vsx is enabled,
and 3 kinds of register class when VSX is NOT enabled.

It runs on POWER target, it makes big(+~30%) performance improvement in one specific bmk(503.bwaves_r) of spec2017 and no other obvious degressions.

Differential revision: https://reviews.llvm.org/D67148

llvm-svn: 374634
2019-10-12 02:53:04 +00:00
..
Disassembler Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
MCTargetDesc Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
TargetInfo Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
CMakeLists.txt [XCore] Move InstPrinter files to MCTargetDesc. NFC 2019-05-10 23:36:49 +00:00
LLVMBuild.txt [XCore] Move InstPrinter files to MCTargetDesc. NFC 2019-05-10 23:36:49 +00:00
README.txt
XCore.h
XCore.td
XCoreAsmPrinter.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
XCoreCallingConv.td
XCoreFrameLowering.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
XCoreFrameLowering.h
XCoreFrameToArgsOffsetElim.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
XCoreISelDAGToDAG.cpp
XCoreISelLowering.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
XCoreISelLowering.h Seperate volatility and atomicity/ordering in SelectionDAG 2019-02-27 20:20:08 +00:00
XCoreInstrFormats.td
XCoreInstrInfo.cpp
XCoreInstrInfo.h
XCoreInstrInfo.td
XCoreLowerThreadLocal.cpp
XCoreMCInstLower.cpp
XCoreMCInstLower.h
XCoreMachineFunctionInfo.cpp
XCoreMachineFunctionInfo.h
XCoreRegisterInfo.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
XCoreRegisterInfo.h CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
XCoreRegisterInfo.td
XCoreSelectionDAGInfo.cpp
XCoreSelectionDAGInfo.h
XCoreSubtarget.cpp
XCoreSubtarget.h
XCoreTargetMachine.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
XCoreTargetMachine.h
XCoreTargetObjectFile.cpp
XCoreTargetObjectFile.h
XCoreTargetStreamer.h
XCoreTargetTransformInfo.h recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure separately in loop-vectorize 2019-10-12 02:53:04 +00:00

README.txt

To-do
-----

* Instruction encodings
* Tailcalls
* Investigate loop alignment
* Add builtins