llvm-project

History

Kai Luo fec7da8285 [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register Summary: When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check if `extsw`'s second operand is a virtual register, otherwise we might get miscompile. Differential Revision: https://reviews.llvm.org/D65315 llvm-svn: 367645		2019-08-02 03:14:17 +00:00
..
AArch64	Rename ExpandISelPseudo->FinalizeISel, delay register reservation	2019-06-19 00:25:39 +00:00
AMDGPU	AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructions	2019-07-29 16:40:58 +00:00
ARM	…
Generic	Rename ExpandISelPseudo->FinalizeISel, delay register reservation	2019-06-19 00:25:39 +00:00
Hexagon	…
Mips	…
NVPTX	…
PowerPC	[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register	2019-08-02 03:14:17 +00:00
WebAssembly	…
X86	[MachineFunction] Base support for call site info tracking	2019-06-27 07:48:06 +00:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.