forked from OSchip/llvm-project
19422 lines
1.3 MiB
19422 lines
1.3 MiB
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// Test host codegen.
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// Test host codegen.
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// We have 8 target regions, but only 7 that actually will generate offloading
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// code, only 6 will have mapped arguments, and only 4 have all-constant map
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// sizes.
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// Check target registration is registered as a Ctor.
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template<typename tx, typename ty>
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struct TT{
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tx X;
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ty Y;
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};
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long long get_val() { return 0; }
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int foo(int n) {
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int a = 0;
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short aa = 0;
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float b[10];
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float bn[n];
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double c[5][10];
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double cn[5][n];
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TT<long long, char> d;
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#pragma omp target parallel for
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for (int i = 3; i < 32; i += 5) {
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#pragma omp cancel for
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#pragma omp cancellation point for
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}
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long long k = get_val();
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#pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic)
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for (int i = 10; i > 1; i--) {
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a += 1;
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}
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// CEHCK-32: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0
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// CEHCK-32: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8*
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// CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false)
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// CEHCK-32: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1
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// CEHCK-32: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8*
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// CEHCK-32: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8*
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// CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false)
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// CEHCK-32: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2
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// CEHCK-32: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8*
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// CEHCK-32: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8*
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// CEHCK-32: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false)
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// CEHCK-64: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 0
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// CEHCK-64: [[FPBPADDR:%.+]] = bitcast [3 x i8*]* [[FPBPGEP]] to i8*
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// CEHCK-64: [[BPCAST:%.+]] = bitcast i8** [[BPGEP]] to i8*
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// CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPBPADDR]], i8* align 8 [[BPCAST]], i64 24, i1 false)
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// CEHCK-64: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 1
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// CEHCK-64: [[FPPADDR:%.+]] = bitcast [3 x i8*]* [[FPPGEP]] to i8*
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// CEHCK-64: [[PCAST:%.+]] = bitcast i8** [[PGEP]] to i8*
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// CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPPADDR]], i8* align 8 [[BCAST]], i64 24, i1 false)
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// CEHCK-64: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], [[KMP_PRIVATES_T]]* [[KMP_PRIVATES]], i32 0, i32 2
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// CEHCK-64: [[FPSIZEADDR:%.+]] = bitcast [3 x i64]* [[FPSIZEGEP]] to i8*
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// CEHCK-64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[FPSIZEADDR]], i8* align 8 bitcast ([3 x i64]* [[SIZET2]] to i8*), i64 24, i1 false)
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int lin = 12;
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#pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait
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for (unsigned long long it = 2000; it >= 600; it-=400) {
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aa += 1;
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}
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#pragma omp target parallel for if(target: n>10)
|
|
for (short it = 6; it <= 20; it-=-4) {
|
|
a += 1;
|
|
aa += 1;
|
|
}
|
|
|
|
// We capture 3 VLA sizes in this target region
|
|
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|
|
// The names below are not necessarily consistent with the names used for the
|
|
// addresses above as some are repeated.
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#pragma omp target parallel for if(target: n>20) schedule(static, a)
|
|
for (unsigned char it = 'z'; it >= 'a'; it+=-1) {
|
|
a += 1;
|
|
b[2] += 1.0;
|
|
bn[3] += 1.0;
|
|
c[1][2] += 1.0;
|
|
cn[1][3] += 1.0;
|
|
d.X += 1;
|
|
d.Y += 1;
|
|
}
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|
|
|
return a;
|
|
}
|
|
|
|
// Check that the offloading functions are emitted and that the arguments are
|
|
// correct and loaded correctly for the target regions in foo().
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|
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|
|
// Create stack storage and store argument in there.
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|
|
// Create stack storage and store argument in there.
|
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|
|
// Create stack storage and store argument in there.
|
|
|
|
// Create local storage for each capture.
|
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|
|
// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
|
|
|
|
template<typename tx>
|
|
tx ftemplate(int n) {
|
|
tx a = 0;
|
|
short aa = 0;
|
|
tx b[10];
|
|
|
|
#pragma omp target parallel for if(target: n>40)
|
|
for (long long i = -10; i < 10; i += 3) {
|
|
a += 1;
|
|
aa += 1;
|
|
b[2] += 1;
|
|
}
|
|
|
|
return a;
|
|
}
|
|
|
|
static
|
|
int fstatic(int n) {
|
|
int a = 0;
|
|
short aa = 0;
|
|
char aaa = 0;
|
|
int b[10];
|
|
|
|
#pragma omp target parallel for if(target: n>50)
|
|
for (unsigned i=100; i<10; i+=10) {
|
|
a += 1;
|
|
aa += 1;
|
|
aaa += 1;
|
|
b[2] += 1;
|
|
}
|
|
|
|
return a;
|
|
}
|
|
|
|
struct S1 {
|
|
double a;
|
|
|
|
int r1(int n){
|
|
int b = n+1;
|
|
short int c[2][n];
|
|
|
|
#pragma omp target parallel for if(target: n>60)
|
|
for (unsigned long long it = 2000; it >= 600; it -= 400) {
|
|
this->a = (double)b + 1.5;
|
|
c[1][1] = ++a;
|
|
}
|
|
|
|
return c[1][1] + (int)b;
|
|
}
|
|
};
|
|
|
|
int bar(int n){
|
|
int a = 0;
|
|
|
|
a += foo(n);
|
|
|
|
S1 S;
|
|
a += S.r1(n);
|
|
|
|
a += fstatic(n);
|
|
|
|
a += ftemplate<int>(n);
|
|
|
|
return a;
|
|
}
|
|
|
|
|
|
|
|
// We capture 2 VLA sizes in this target region
|
|
|
|
|
|
// The names below are not necessarily consistent with the names used for the
|
|
// addresses above as some are repeated.
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
// Check that the offloading functions are emitted and that the arguments are
|
|
// correct and loaded correctly for the target regions of the callees of bar().
|
|
|
|
// Create local storage for each capture.
|
|
// Store captures in the context.
|
|
|
|
|
|
// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
|
|
|
|
|
|
// Create local storage for each capture.
|
|
// Store captures in the context.
|
|
|
|
|
|
|
|
|
|
// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
|
|
|
|
// Create local storage for each capture.
|
|
// Store captures in the context.
|
|
|
|
|
|
|
|
// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
|
|
|
|
|
|
#endif
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP28]], align 8
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
|
|
// CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
|
|
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
|
|
// CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
|
|
// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
|
|
// CHECK1-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
|
|
// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
|
|
// CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8
|
|
// CHECK1-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
|
|
// CHECK1-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4
|
|
// CHECK1-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
|
|
// CHECK1-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2
|
|
// CHECK1-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
|
|
// CHECK1-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8
|
|
// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8
|
|
// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP70]], align 8
|
|
// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8
|
|
// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8
|
|
// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP75]], align 8
|
|
// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
|
// CHECK1: omp_offload.failed13:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
|
// CHECK1: omp_offload.cont14:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4
|
|
// CHECK1-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK1-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4
|
|
// CHECK1-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
|
|
// CHECK1-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
|
|
// CHECK1: omp_if.then19:
|
|
// CHECK1-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK1-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK1-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
|
|
// CHECK1-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false)
|
|
// CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8
|
|
// CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8
|
|
// CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP94]], align 8
|
|
// CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
|
|
// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
|
|
// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP99]], align 8
|
|
// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8
|
|
// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8
|
|
// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP104]], align 8
|
|
// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK1-NEXT: store float* [[VLA]], float** [[TMP106]], align 8
|
|
// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
|
|
// CHECK1-NEXT: store float* [[VLA]], float** [[TMP108]], align 8
|
|
// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK1-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8
|
|
// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP110]], align 8
|
|
// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8
|
|
// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
|
|
// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
|
|
// CHECK1-NEXT: store i64 5, i64* [[TMP117]], align 8
|
|
// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK1-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64*
|
|
// CHECK1-NEXT: store i64 5, i64* [[TMP119]], align 8
|
|
// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP120]], align 8
|
|
// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK1-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8
|
|
// CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK1-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8
|
|
// CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP125]], align 8
|
|
// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK1-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8
|
|
// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK1-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double**
|
|
// CHECK1-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8
|
|
// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK1-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8
|
|
// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP131]], align 8
|
|
// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK1-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8
|
|
// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT**
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8
|
|
// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP136]], align 8
|
|
// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8
|
|
// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK1-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8
|
|
// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP141]], align 8
|
|
// CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK1: omp_offload.failed23:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK1: omp_offload.cont24:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK1: omp_if.else25:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK1: omp_if.end26:
|
|
// CHECK1-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP148]])
|
|
// CHECK1-NEXT: ret i32 [[TMP147]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK1: .cancel.exit:
|
|
// CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK1: .cancel.continue:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK1: .cancel.exit2:
|
|
// CHECK1-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK1: .cancel.continue3:
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK1: cancel.cont:
|
|
// CHECK1-NEXT: ret void
|
|
// CHECK1: cancel.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK1: omp.dispatch.cond:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK1: omp.dispatch.body:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK1: omp.dispatch.inc:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK1: omp.dispatch.end:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK1: .omp.linear.pu:
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK1: .omp.linear.pu.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK1: .omp.linear.pu:
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK1: .omp.linear.pu.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
|
|
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
|
|
// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
|
|
// CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
|
|
// CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK1: omp_offload.failed.i:
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK1-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK1: .omp_outlined..3.exit:
|
|
// CHECK1-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK1: omp.dispatch.cond:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK1: omp.dispatch.body:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK1: omp.dispatch.inc:
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK1: omp.dispatch.end:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false)
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
|
|
// CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]]
|
|
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]]
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK1-NEXT: ret i32 [[ADD4]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK1-SAME: () #[[ATTR6]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK2-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK2-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK2-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8
|
|
// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8
|
|
// CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4
|
|
// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4
|
|
// CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4
|
|
// CHECK2-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK2-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
|
|
// CHECK2-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
|
|
// CHECK2-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
|
|
// CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
|
|
// CHECK2-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
|
|
// CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
|
|
// CHECK2-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
|
|
// CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
|
|
// CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8
|
|
// CHECK2-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
|
|
// CHECK2-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4
|
|
// CHECK2-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
|
|
// CHECK2-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2
|
|
// CHECK2-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
|
|
// CHECK2-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8
|
|
// CHECK2-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8
|
|
// CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP70]], align 8
|
|
// CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8
|
|
// CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8
|
|
// CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP75]], align 8
|
|
// CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
|
// CHECK2: omp_offload.failed13:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
|
// CHECK2: omp_offload.cont14:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4
|
|
// CHECK2-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK2-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK2-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4
|
|
// CHECK2-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
|
|
// CHECK2-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
|
|
// CHECK2: omp_if.then19:
|
|
// CHECK2-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK2-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK2-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
|
|
// CHECK2-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false)
|
|
// CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8
|
|
// CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8
|
|
// CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP94]], align 8
|
|
// CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
|
|
// CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
|
|
// CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP99]], align 8
|
|
// CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8
|
|
// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8
|
|
// CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP104]], align 8
|
|
// CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK2-NEXT: store float* [[VLA]], float** [[TMP106]], align 8
|
|
// CHECK2-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
|
|
// CHECK2-NEXT: store float* [[VLA]], float** [[TMP108]], align 8
|
|
// CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK2-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8
|
|
// CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP110]], align 8
|
|
// CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8
|
|
// CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
|
|
// CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK2-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
|
|
// CHECK2-NEXT: store i64 5, i64* [[TMP117]], align 8
|
|
// CHECK2-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK2-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64*
|
|
// CHECK2-NEXT: store i64 5, i64* [[TMP119]], align 8
|
|
// CHECK2-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP120]], align 8
|
|
// CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK2-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8
|
|
// CHECK2-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK2-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8
|
|
// CHECK2-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP125]], align 8
|
|
// CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK2-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8
|
|
// CHECK2-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK2-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double**
|
|
// CHECK2-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8
|
|
// CHECK2-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK2-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8
|
|
// CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP131]], align 8
|
|
// CHECK2-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK2-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8
|
|
// CHECK2-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK2-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT**
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8
|
|
// CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP136]], align 8
|
|
// CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK2-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8
|
|
// CHECK2-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK2-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8
|
|
// CHECK2-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP141]], align 8
|
|
// CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK2: omp_offload.failed23:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK2: omp_offload.cont24:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK2: omp_if.else25:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK2: omp_if.end26:
|
|
// CHECK2-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP148]])
|
|
// CHECK2-NEXT: ret i32 [[TMP147]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK2-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK2: .cancel.exit:
|
|
// CHECK2-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK2: .cancel.continue:
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK2: .cancel.exit2:
|
|
// CHECK2-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK2: .cancel.continue3:
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK2-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK2: cancel.cont:
|
|
// CHECK2-NEXT: ret void
|
|
// CHECK2: cancel.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK2-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK2: omp.dispatch.cond:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK2: omp.dispatch.body:
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK2-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK2: omp.dispatch.inc:
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK2: omp.dispatch.end:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK2: .omp.linear.pu:
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8
|
|
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK2: .omp.linear.pu.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK2-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK2-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK2-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK2-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK2-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK2-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK2-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK2-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK2-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK2-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK2-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK2: .omp.linear.pu:
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK2: .omp.linear.pu.done:
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
|
|
// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
|
|
// CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK2-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
|
|
// CHECK2-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK2-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
|
|
// CHECK2-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK2-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK2-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK2-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK2-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK2-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
|
|
// CHECK2-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
|
|
// CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
|
|
// CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK2: omp_offload.failed.i:
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK2-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK2-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK2-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK2: .omp_outlined..3.exit:
|
|
// CHECK2-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK2-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK2: omp.dispatch.cond:
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK2: omp.dispatch.body:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK2-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK2-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK2-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK2-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK2-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK2-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK2-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK2-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK2-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK2-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK2-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK2-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK2-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK2-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK2-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK2-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK2: omp.dispatch.inc:
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK2-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK2-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK2-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK2: omp.dispatch.end:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK2-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false)
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK2-NEXT: store double* [[A]], double** [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK2-NEXT: store i64 2, i64* [[TMP22]], align 8
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
|
|
// CHECK2-NEXT: store i64 2, i64* [[TMP24]], align 8
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 8
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8
|
|
// CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8
|
|
// CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8
|
|
// CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP36]], align 8
|
|
// CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]]
|
|
// CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK2-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]]
|
|
// CHECK2-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK2-NEXT: ret i32 [[ADD4]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK2-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK2: omp_offload.failed:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK2: omp_offload.cont:
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK2-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK2-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK2-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK2-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK2-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK2-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK2-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK2: cond.true:
|
|
// CHECK2-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK2: cond.false:
|
|
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: br label [[COND_END]]
|
|
// CHECK2: cond.end:
|
|
// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK2-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK2: omp.inner.for.cond:
|
|
// CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK2: omp.inner.for.body:
|
|
// CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK2-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK2-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK2-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK2-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK2: omp.body.continue:
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK2: omp.inner.for.inc:
|
|
// CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK2-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK2: omp.inner.for.end:
|
|
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK2: omp.loop.exit:
|
|
// CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK2-SAME: () #[[ATTR6]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP29]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
|
|
// CHECK3-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK3-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
|
|
// CHECK3-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
|
|
// CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
|
|
// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
|
|
// CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
|
|
// CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
|
|
// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
|
|
// CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
|
|
// CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4
|
|
// CHECK3-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
|
|
// CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
|
|
// CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK3-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2
|
|
// CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4
|
|
// CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4
|
|
// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP66]], align 4
|
|
// CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4
|
|
// CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4
|
|
// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK3: omp_offload.failed9:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK3: omp_offload.cont10:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
|
|
// CHECK3-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK3-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
|
|
// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK3: omp_if.then13:
|
|
// CHECK3-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK3-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
|
|
// CHECK3-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK3-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
|
|
// CHECK3-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
|
|
// CHECK3-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false)
|
|
// CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4
|
|
// CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4
|
|
// CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4
|
|
// CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
|
|
// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
|
|
// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP97]], align 4
|
|
// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4
|
|
// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4
|
|
// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP102]], align 4
|
|
// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float**
|
|
// CHECK3-NEXT: store float* [[VLA]], float** [[TMP104]], align 4
|
|
// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK3-NEXT: store float* [[VLA]], float** [[TMP106]], align 4
|
|
// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4
|
|
// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP108]], align 4
|
|
// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]**
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4
|
|
// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
|
|
// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
|
|
// CHECK3-NEXT: store i32 5, i32* [[TMP115]], align 4
|
|
// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
|
|
// CHECK3-NEXT: store i32 5, i32* [[TMP117]], align 4
|
|
// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP118]], align 4
|
|
// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4
|
|
// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4
|
|
// CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP123]], align 4
|
|
// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double**
|
|
// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4
|
|
// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK3-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK3-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4
|
|
// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK3-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4
|
|
// CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP129]], align 4
|
|
// CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK3-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT**
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4
|
|
// CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4
|
|
// CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP134]], align 4
|
|
// CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK3-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4
|
|
// CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4
|
|
// CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP139]], align 4
|
|
// CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK3: omp_offload.failed17:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK3: omp_offload.cont18:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK3: omp_if.else19:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK3: omp_if.end20:
|
|
// CHECK3-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP146]])
|
|
// CHECK3-NEXT: ret i32 [[TMP145]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK3: .cancel.exit:
|
|
// CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK3: .cancel.continue:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK3: .cancel.exit2:
|
|
// CHECK3-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK3: .cancel.continue3:
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK3: cancel.cont:
|
|
// CHECK3-NEXT: ret void
|
|
// CHECK3: cancel.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK3: omp.dispatch.cond:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK3: omp.dispatch.body:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK3: omp.dispatch.inc:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK3: omp.dispatch.end:
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK3: .omp.linear.pu:
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8
|
|
// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK3: .omp.linear.pu.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK3: .omp.linear.pu:
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK3: .omp.linear.pu.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
|
|
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
|
|
// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
|
|
// CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK3: omp_offload.failed.i:
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK3: .omp_outlined..3.exit:
|
|
// CHECK3-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK3: omp.dispatch.cond:
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK3: omp.dispatch.body:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK3: omp.dispatch.inc:
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK3: omp.dispatch.end:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false)
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
|
|
// CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]]
|
|
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]]
|
|
// CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK3-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK3-SAME: () #[[ATTR6]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK4-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK4-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK4-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP29]], align 4
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
|
|
// CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
|
|
// CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
|
|
// CHECK4-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK4-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
|
|
// CHECK4-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
|
|
// CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
|
|
// CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
|
|
// CHECK4-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
|
|
// CHECK4-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
|
|
// CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
|
|
// CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
|
|
// CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4
|
|
// CHECK4-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
|
|
// CHECK4-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
|
|
// CHECK4-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK4-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2
|
|
// CHECK4-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK4-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4
|
|
// CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4
|
|
// CHECK4-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP66]], align 4
|
|
// CHECK4-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4
|
|
// CHECK4-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4
|
|
// CHECK4-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK4-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK4: omp_offload.failed9:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK4: omp_offload.cont10:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
|
|
// CHECK4-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK4-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
|
|
// CHECK4-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK4: omp_if.then13:
|
|
// CHECK4-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK4-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
|
|
// CHECK4-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK4-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
|
|
// CHECK4-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
|
|
// CHECK4-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false)
|
|
// CHECK4-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4
|
|
// CHECK4-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4
|
|
// CHECK4-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP92]], align 4
|
|
// CHECK4-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
|
|
// CHECK4-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
|
|
// CHECK4-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP97]], align 4
|
|
// CHECK4-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4
|
|
// CHECK4-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4
|
|
// CHECK4-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP102]], align 4
|
|
// CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float**
|
|
// CHECK4-NEXT: store float* [[VLA]], float** [[TMP104]], align 4
|
|
// CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK4-NEXT: store float* [[VLA]], float** [[TMP106]], align 4
|
|
// CHECK4-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4
|
|
// CHECK4-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP108]], align 4
|
|
// CHECK4-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]**
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4
|
|
// CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
|
|
// CHECK4-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK4-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK4-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
|
|
// CHECK4-NEXT: store i32 5, i32* [[TMP115]], align 4
|
|
// CHECK4-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK4-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
|
|
// CHECK4-NEXT: store i32 5, i32* [[TMP117]], align 4
|
|
// CHECK4-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP118]], align 4
|
|
// CHECK4-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK4-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4
|
|
// CHECK4-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK4-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4
|
|
// CHECK4-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP123]], align 4
|
|
// CHECK4-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK4-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double**
|
|
// CHECK4-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4
|
|
// CHECK4-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK4-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK4-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4
|
|
// CHECK4-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK4-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4
|
|
// CHECK4-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP129]], align 4
|
|
// CHECK4-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK4-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT**
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4
|
|
// CHECK4-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK4-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4
|
|
// CHECK4-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP134]], align 4
|
|
// CHECK4-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK4-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4
|
|
// CHECK4-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK4-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4
|
|
// CHECK4-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP139]], align 4
|
|
// CHECK4-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK4: omp_offload.failed17:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK4: omp_offload.cont18:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK4: omp_if.else19:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK4: omp_if.end20:
|
|
// CHECK4-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP146]])
|
|
// CHECK4-NEXT: ret i32 [[TMP145]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK4-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK4: .cancel.exit:
|
|
// CHECK4-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK4: .cancel.continue:
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK4: .cancel.exit2:
|
|
// CHECK4-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK4: .cancel.continue3:
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK4-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK4: cancel.cont:
|
|
// CHECK4-NEXT: ret void
|
|
// CHECK4: cancel.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK4-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK4-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK4: omp.dispatch.cond:
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK4: omp.dispatch.body:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK4-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK4: omp.dispatch.inc:
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK4: omp.dispatch.end:
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK4: .omp.linear.pu:
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8
|
|
// CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK4: .omp.linear.pu.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK4-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK4-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK4-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK4-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK4-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK4-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK4-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK4-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK4-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK4-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK4: .omp.linear.pu:
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK4: .omp.linear.pu.done:
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
|
|
// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
|
|
// CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK4-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK4-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
|
|
// CHECK4-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK4-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
|
|
// CHECK4-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK4-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK4-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK4-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK4-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK4-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
|
|
// CHECK4-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
|
|
// CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK4: omp_offload.failed.i:
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK4-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK4: .omp_outlined..3.exit:
|
|
// CHECK4-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK4-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK4: omp.dispatch.cond:
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK4: omp.dispatch.body:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK4-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK4-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK4-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK4-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK4-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK4-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK4-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK4-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK4-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK4-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK4-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK4-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK4-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK4-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK4-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK4-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK4: omp.dispatch.inc:
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK4-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK4-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK4-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK4: omp.dispatch.end:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK4-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false)
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK4-NEXT: store double* [[A]], double** [[TMP14]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK4-NEXT: store i32 2, i32* [[TMP22]], align 4
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
|
|
// CHECK4-NEXT: store i32 2, i32* [[TMP24]], align 4
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP25]], align 4
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4
|
|
// CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK4-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4
|
|
// CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4
|
|
// CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP36]], align 4
|
|
// CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]]
|
|
// CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK4-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]]
|
|
// CHECK4-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK4-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK4: omp_if.then:
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK4: omp_offload.failed:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK4: omp_offload.cont:
|
|
// CHECK4-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK4: omp_if.else:
|
|
// CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK4-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK4: omp_if.end:
|
|
// CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK4-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK4-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK4-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK4-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK4-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK4-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK4: cond.true:
|
|
// CHECK4-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK4: cond.false:
|
|
// CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: br label [[COND_END]]
|
|
// CHECK4: cond.end:
|
|
// CHECK4-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK4-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK4: omp.inner.for.cond:
|
|
// CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK4: omp.inner.for.body:
|
|
// CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK4-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK4-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK4-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK4-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK4-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK4-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK4: omp.body.continue:
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK4: omp.inner.for.inc:
|
|
// CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK4: omp.inner.for.end:
|
|
// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK4: omp.loop.exit:
|
|
// CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK4-SAME: () #[[ATTR6]] {
|
|
// CHECK4-NEXT: entry:
|
|
// CHECK4-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK4-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK9: .cancel.exit:
|
|
// CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK9: .cancel.continue:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK9: .cancel.exit2:
|
|
// CHECK9-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK9: .cancel.continue3:
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK9: cancel.cont:
|
|
// CHECK9-NEXT: ret void
|
|
// CHECK9: cancel.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK9-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK9-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK9-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK9-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK9-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK9-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK9-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK9: .omp.linear.pu:
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK9: .omp.linear.pu.done:
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK9-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK9-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK9-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK9: omp.dispatch.cond:
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK9: omp.dispatch.body:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK9-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK9-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK9-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK9-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK9-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK9-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK9-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK9-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK9-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK9-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK9-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK9-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK9-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK9-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK9: omp.dispatch.inc:
|
|
// CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK9-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK9-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK9: omp.dispatch.end:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK9-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK10-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK10: .cancel.exit:
|
|
// CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK10: .cancel.continue:
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK10: .cancel.exit2:
|
|
// CHECK10-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK10: .cancel.continue3:
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK10-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK10: cancel.cont:
|
|
// CHECK10-NEXT: ret void
|
|
// CHECK10: cancel.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK10-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK10-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK10-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK10-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK10-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK10-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK10-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK10-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK10-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK10-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK10-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK10-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK10-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK10-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK10-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK10-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK10-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK10: .omp.linear.pu:
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK10-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK10: .omp.linear.pu.done:
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK10-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK10-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK10-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK10-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK10-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK10: omp.dispatch.cond:
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK10-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK10: omp.dispatch.body:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK10-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK10-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK10-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK10-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK10-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK10-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK10-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK10-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK10-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK10-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK10-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK10-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK10-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK10-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK10-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK10-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK10-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK10-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK10-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK10-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK10-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK10-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK10: omp.dispatch.inc:
|
|
// CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK10-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK10-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK10-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK10-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK10: omp.dispatch.end:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK10-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK10-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK10-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK10-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK10-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK10-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK10-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK10-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK10-NEXT: entry:
|
|
// CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK10-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK10-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK10: cond.true:
|
|
// CHECK10-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK10: cond.false:
|
|
// CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: br label [[COND_END]]
|
|
// CHECK10: cond.end:
|
|
// CHECK10-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK10-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK10-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK10: omp.inner.for.cond:
|
|
// CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK10-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK10-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK10: omp.inner.for.body:
|
|
// CHECK10-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK10-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK10-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK10-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK10-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK10-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK10-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK10-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK10: omp.body.continue:
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK10: omp.inner.for.inc:
|
|
// CHECK10-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK10-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK10: omp.inner.for.end:
|
|
// CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK10: omp.loop.exit:
|
|
// CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK10-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK11: .cancel.exit:
|
|
// CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK11: .cancel.continue:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK11: .cancel.exit2:
|
|
// CHECK11-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK11: .cancel.continue3:
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK11: cancel.cont:
|
|
// CHECK11-NEXT: ret void
|
|
// CHECK11: cancel.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK11-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK11-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK11-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK11-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK11-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK11: .omp.linear.pu:
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK11: .omp.linear.pu.done:
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK11-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK11: omp.dispatch.cond:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK11: omp.dispatch.body:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK11-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK11-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK11-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK11-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK11-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK11: omp.dispatch.inc:
|
|
// CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK11-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK11-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK11: omp.dispatch.end:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK11-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK12: .cancel.exit:
|
|
// CHECK12-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK12: .cancel.continue:
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK12: .cancel.exit2:
|
|
// CHECK12-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK12: .cancel.continue3:
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK12-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK12: cancel.cont:
|
|
// CHECK12-NEXT: ret void
|
|
// CHECK12: cancel.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK12-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK12-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK12-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK12-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK12-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK12-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK12-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK12-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK12-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK12-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK12-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK12-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK12-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK12-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK12-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK12-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK12-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK12-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK12: .omp.linear.pu:
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK12: .omp.linear.pu.done:
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK12-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK12-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK12-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK12: omp.dispatch.cond:
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK12: omp.dispatch.body:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK12-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK12-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK12-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK12-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK12-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK12-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK12-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK12-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK12-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK12-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK12-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK12-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK12-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK12-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK12-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK12-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK12-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK12-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK12-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK12-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK12-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK12-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK12-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK12: omp.dispatch.inc:
|
|
// CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK12-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK12-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK12-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK12-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK12: omp.dispatch.end:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK12-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK12-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK12-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK12-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK12-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK12-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK12-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK12-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK12-NEXT: entry:
|
|
// CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK12-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK12-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK12: cond.true:
|
|
// CHECK12-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK12: cond.false:
|
|
// CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: br label [[COND_END]]
|
|
// CHECK12: cond.end:
|
|
// CHECK12-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK12-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK12: omp.inner.for.cond:
|
|
// CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK12: omp.inner.for.body:
|
|
// CHECK12-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK12-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK12-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK12-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK12-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK12-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK12: omp.body.continue:
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK12: omp.inner.for.inc:
|
|
// CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK12-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK12: omp.inner.for.end:
|
|
// CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK12: omp.loop.exit:
|
|
// CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK12-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK17-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK17-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK17-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP28]], align 8
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4
|
|
// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4
|
|
// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4
|
|
// CHECK17-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
|
|
// CHECK17-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
|
|
// CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
|
|
// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
|
|
// CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
|
|
// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
|
|
// CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
|
|
// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
|
|
// CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8
|
|
// CHECK17-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
|
|
// CHECK17-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4
|
|
// CHECK17-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
|
|
// CHECK17-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2
|
|
// CHECK17-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
|
|
// CHECK17-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8
|
|
// CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8
|
|
// CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP70]], align 8
|
|
// CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8
|
|
// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8
|
|
// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8
|
|
// CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK17-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
|
// CHECK17: omp_offload.failed13:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
|
// CHECK17: omp_offload.cont14:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4
|
|
// CHECK17-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK17-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4
|
|
// CHECK17-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
|
|
// CHECK17-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
|
|
// CHECK17: omp_if.then19:
|
|
// CHECK17-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK17-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK17-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
|
|
// CHECK17-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false)
|
|
// CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8
|
|
// CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8
|
|
// CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP94]], align 8
|
|
// CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
|
|
// CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
|
|
// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
|
|
// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP99]], align 8
|
|
// CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8
|
|
// CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8
|
|
// CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP104]], align 8
|
|
// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK17-NEXT: store float* [[VLA]], float** [[TMP106]], align 8
|
|
// CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
|
|
// CHECK17-NEXT: store float* [[VLA]], float** [[TMP108]], align 8
|
|
// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK17-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8
|
|
// CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP110]], align 8
|
|
// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK17-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8
|
|
// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
|
|
// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
|
|
// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK17-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
|
|
// CHECK17-NEXT: store i64 5, i64* [[TMP117]], align 8
|
|
// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK17-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64*
|
|
// CHECK17-NEXT: store i64 5, i64* [[TMP119]], align 8
|
|
// CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP120]], align 8
|
|
// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK17-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8
|
|
// CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK17-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8
|
|
// CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP125]], align 8
|
|
// CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK17-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8
|
|
// CHECK17-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK17-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double**
|
|
// CHECK17-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8
|
|
// CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK17-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8
|
|
// CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP131]], align 8
|
|
// CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK17-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8
|
|
// CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK17-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT**
|
|
// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8
|
|
// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP136]], align 8
|
|
// CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK17-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8
|
|
// CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK17-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8
|
|
// CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP141]], align 8
|
|
// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK17-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK17: omp_offload.failed23:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK17: omp_offload.cont24:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK17: omp_if.else25:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK17: omp_if.end26:
|
|
// CHECK17-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP148]])
|
|
// CHECK17-NEXT: ret i32 [[TMP147]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK17-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK17: .cancel.exit:
|
|
// CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK17: .cancel.continue:
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK17: .cancel.exit2:
|
|
// CHECK17-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK17: .cancel.continue3:
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK17: cancel.cont:
|
|
// CHECK17-NEXT: ret void
|
|
// CHECK17: cancel.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK17: omp.dispatch.cond:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK17: omp.dispatch.body:
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK17-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK17-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK17: omp.dispatch.inc:
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK17: omp.dispatch.end:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK17: .omp.linear.pu:
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK17: .omp.linear.pu.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK17: .omp.linear.pu:
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK17: .omp.linear.pu.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
|
|
// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
|
|
// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
|
|
// CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
|
|
// CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK17: omp_offload.failed.i:
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK17-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK17: .omp_outlined..3.exit:
|
|
// CHECK17-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK17: omp.dispatch.cond:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK17: omp.dispatch.body:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK17: omp.dispatch.inc:
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK17: omp.dispatch.end:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false)
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
|
|
// CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8
|
|
// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8
|
|
// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8
|
|
// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]]
|
|
// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]]
|
|
// CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK17-NEXT: ret i32 [[ADD4]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK17-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK17-SAME: () #[[ATTR6]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK18-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK18-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK18-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = icmp ne i32 [[TMP7]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP8]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK18-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[K]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP11]], i64* [[K_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP10]], i64 [[TMP12]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP15]], i32* [[CONV3]], align 4
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP17]], i32* [[CONV5]], align 4
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = load i64, i64* [[A_CASTED4]], align 8
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP20]], align 8
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP22]], align 8
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP25]], align 8
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP16]], i64* [[TMP27]], align 8
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP28]], align 8
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP30]], align 8
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP18]], i64* [[TMP32]], align 8
|
|
// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8
|
|
// CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP37:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: store i16 [[TMP37]], i16* [[TMP36]], align 4
|
|
// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP39:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP39]], i32* [[TMP38]], align 4
|
|
// CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP41]], i32* [[TMP40]], align 4
|
|
// CHECK18-NEXT: [[TMP42:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP42]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP44]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP46:%.*]] = load i8*, i8** [[TMP45]], align 8
|
|
// CHECK18-NEXT: [[TMP47:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP46]], i8* align 4 [[TMP47]], i64 12, i1 false)
|
|
// CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP43]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8* [[TMP46]] to %struct.anon*
|
|
// CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP51:%.*]] = bitcast [3 x i8*]* [[TMP50]] to i8*
|
|
// CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP34]] to i8*
|
|
// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP51]], i8* align 8 [[TMP52]], i64 24, i1 false)
|
|
// CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP54:%.*]] = bitcast [3 x i8*]* [[TMP53]] to i8*
|
|
// CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP35]] to i8*
|
|
// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP54]], i8* align 8 [[TMP55]], i64 24, i1 false)
|
|
// CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP57:%.*]] = bitcast [3 x i64]* [[TMP56]] to i8*
|
|
// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP57]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false)
|
|
// CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP48]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: store i16 [[TMP59]], i16* [[TMP58]], align 8
|
|
// CHECK18-NEXT: [[TMP60:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP42]])
|
|
// CHECK18-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP61]], i32* [[CONV7]], align 4
|
|
// CHECK18-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED6]], align 8
|
|
// CHECK18-NEXT: [[TMP63:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP63]], i16* [[CONV9]], align 2
|
|
// CHECK18-NEXT: [[TMP64:%.*]] = load i64, i64* [[AA_CASTED8]], align 8
|
|
// CHECK18-NEXT: [[TMP65:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK18: omp_if.then:
|
|
// CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP67]], align 8
|
|
// CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8
|
|
// CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP70]], align 8
|
|
// CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP72]], align 8
|
|
// CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP64]], i64* [[TMP74]], align 8
|
|
// CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8
|
|
// CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP78:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP76]], i8** [[TMP77]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK18-NEXT: [[TMP79:%.*]] = icmp ne i32 [[TMP78]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP79]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]]
|
|
// CHECK18: omp_offload.failed13:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT14]]
|
|
// CHECK18: omp_offload.cont14:
|
|
// CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK18: omp_if.else:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i64 [[TMP62]], i64 [[TMP64]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK18: omp_if.end:
|
|
// CHECK18-NEXT: [[TMP80:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP80]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[TMP81:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP81]], i32* [[CONV16]], align 4
|
|
// CHECK18-NEXT: [[TMP82:%.*]] = load i64, i64* [[A_CASTED15]], align 8
|
|
// CHECK18-NEXT: [[TMP83:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK18-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP83]], i32* [[CONV17]], align 4
|
|
// CHECK18-NEXT: [[TMP84:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP85:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP85]], 20
|
|
// CHECK18-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]]
|
|
// CHECK18: omp_if.then19:
|
|
// CHECK18-NEXT: [[TMP86:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK18-NEXT: [[TMP87:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK18-NEXT: [[TMP88:%.*]] = mul nuw i64 [[TMP87]], 8
|
|
// CHECK18-NEXT: [[TMP89:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP89]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false)
|
|
// CHECK18-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP91]], align 8
|
|
// CHECK18-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP82]], i64* [[TMP93]], align 8
|
|
// CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP94]], align 8
|
|
// CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 8
|
|
// CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to [10 x float]**
|
|
// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP98]], align 8
|
|
// CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP99]], align 8
|
|
// CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP101]], align 8
|
|
// CHECK18-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP103]], align 8
|
|
// CHECK18-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP104]], align 8
|
|
// CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK18-NEXT: store float* [[VLA]], float** [[TMP106]], align 8
|
|
// CHECK18-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to float**
|
|
// CHECK18-NEXT: store float* [[VLA]], float** [[TMP108]], align 8
|
|
// CHECK18-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK18-NEXT: store i64 [[TMP86]], i64* [[TMP109]], align 8
|
|
// CHECK18-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP110]], align 8
|
|
// CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
|
|
// CHECK18-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 8
|
|
// CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
|
|
// CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to [5 x [10 x double]]**
|
|
// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP114]], align 8
|
|
// CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP115]], align 8
|
|
// CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
|
|
// CHECK18-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64*
|
|
// CHECK18-NEXT: store i64 5, i64* [[TMP117]], align 8
|
|
// CHECK18-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
|
|
// CHECK18-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64*
|
|
// CHECK18-NEXT: store i64 5, i64* [[TMP119]], align 8
|
|
// CHECK18-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP120]], align 8
|
|
// CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
|
|
// CHECK18-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP122]], align 8
|
|
// CHECK18-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
|
|
// CHECK18-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP124]], align 8
|
|
// CHECK18-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP125]], align 8
|
|
// CHECK18-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
|
|
// CHECK18-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP127]], align 8
|
|
// CHECK18-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
|
|
// CHECK18-NEXT: [[TMP129:%.*]] = bitcast i8** [[TMP128]] to double**
|
|
// CHECK18-NEXT: store double* [[VLA1]], double** [[TMP129]], align 8
|
|
// CHECK18-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK18-NEXT: store i64 [[TMP88]], i64* [[TMP130]], align 8
|
|
// CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP131]], align 8
|
|
// CHECK18-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
|
|
// CHECK18-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 8
|
|
// CHECK18-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
|
|
// CHECK18-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to %struct.TT**
|
|
// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP135]], align 8
|
|
// CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP136]], align 8
|
|
// CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9
|
|
// CHECK18-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP138]], align 8
|
|
// CHECK18-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9
|
|
// CHECK18-NEXT: [[TMP140:%.*]] = bitcast i8** [[TMP139]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP84]], i64* [[TMP140]], align 8
|
|
// CHECK18-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP141]], align 8
|
|
// CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP144:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP142]], i8** [[TMP143]], i64* [[TMP144]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK18-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]]
|
|
// CHECK18: omp_offload.failed23:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT24]]
|
|
// CHECK18: omp_offload.cont24:
|
|
// CHECK18-NEXT: br label [[OMP_IF_END26:%.*]]
|
|
// CHECK18: omp_if.else25:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i64 [[TMP82]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP84]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_IF_END26]]
|
|
// CHECK18: omp_if.end26:
|
|
// CHECK18-NEXT: [[TMP147:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP148:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP148]])
|
|
// CHECK18-NEXT: ret i32 [[TMP147]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK18-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK18-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK18: .cancel.exit:
|
|
// CHECK18-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK18: .cancel.continue:
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK18: .cancel.exit2:
|
|
// CHECK18-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK18: .cancel.continue3:
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK18-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK18: cancel.cont:
|
|
// CHECK18-NEXT: ret void
|
|
// CHECK18: cancel.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK18-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK18-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK18: omp.dispatch.cond:
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK18-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK18: omp.dispatch.body:
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK18-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]]
|
|
// CHECK18-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK18: omp.dispatch.inc:
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK18: omp.dispatch.end:
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK18: .omp.linear.pu:
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP14]], i64* [[K_ADDR]], align 8
|
|
// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK18: .omp.linear.pu.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK18-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK18-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK18-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK18-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK18-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK18-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK18-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK18-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK18-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK18-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK18-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK18-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK18-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK18-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK18: .omp.linear.pu:
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK18: .omp.linear.pu.done:
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8
|
|
// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8
|
|
// CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8
|
|
// CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8
|
|
// CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8
|
|
// CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8
|
|
// CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8
|
|
// CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8
|
|
// CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8
|
|
// CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
|
|
// CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
|
|
// CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
|
|
// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8
|
|
// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8
|
|
// CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
|
|
// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
|
|
// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
|
|
// CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK18: omp_offload.failed.i:
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !24
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[LIN_CASTED_I]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP29]], i32* [[CONV4_I]], align 4, !noalias !24
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[LIN_CASTED_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK18-NEXT: [[CONV5_I:%.*]] = bitcast i64* [[A_CASTED_I]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV5_I]], align 4, !noalias !24
|
|
// CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[A_CASTED_I]], align 8, !noalias !24
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i64 [[TMP28]], i64 [[TMP30]], i64 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK18: .omp_outlined..3.exit:
|
|
// CHECK18-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK18-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK18-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK18: omp.dispatch.cond:
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK18-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK18: omp.dispatch.body:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK18-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK18-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK18-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK18-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK18-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK18-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK18-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK18-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK18-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK18-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK18-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK18-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK18-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK18-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK18-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK18-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK18-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK18: omp.dispatch.inc:
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK18-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK18-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK18-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK18: omp.dispatch.end:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8
|
|
// CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK18: omp_if.then:
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false)
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK18-NEXT: store double* [[A]], double** [[TMP14]], align 8
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64*
|
|
// CHECK18-NEXT: store i64 2, i64* [[TMP22]], align 8
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64*
|
|
// CHECK18-NEXT: store i64 2, i64* [[TMP24]], align 8
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8
|
|
// CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8
|
|
// CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8
|
|
// CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP36]], align 8
|
|
// CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK18-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK18: omp_if.else:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK18: omp_if.end:
|
|
// CHECK18-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]]
|
|
// CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK18-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]]
|
|
// CHECK18-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
|
|
// CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK18-NEXT: ret i32 [[ADD4]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK18: omp_if.then:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
|
|
// CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8
|
|
// CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK18: omp_if.else:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK18: omp_if.end:
|
|
// CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
|
|
// CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK18-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK18: omp_if.then:
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
|
|
// CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
|
|
// CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
|
|
// CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8
|
|
// CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK18: omp_offload.failed:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK18: omp_offload.cont:
|
|
// CHECK18-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK18: omp_if.else:
|
|
// CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK18-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK18: omp_if.end:
|
|
// CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK18-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK18-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK18-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK18-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK18-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK18-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK18-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK18-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK18-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK18-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK18-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK18-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK18-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK18: cond.true:
|
|
// CHECK18-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK18: cond.false:
|
|
// CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: br label [[COND_END]]
|
|
// CHECK18: cond.end:
|
|
// CHECK18-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK18-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK18-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK18: omp.inner.for.cond:
|
|
// CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK18-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK18-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK18: omp.inner.for.body:
|
|
// CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK18-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK18-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK18-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK18-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK18-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK18-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK18-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK18-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK18: omp.body.continue:
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK18: omp.inner.for.inc:
|
|
// CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK18-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK18-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK18: omp.inner.for.end:
|
|
// CHECK18-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK18: omp.loop.exit:
|
|
// CHECK18-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK18-SAME: () #[[ATTR6]] {
|
|
// CHECK18-NEXT: entry:
|
|
// CHECK18-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK18-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK19-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK19-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP29]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
|
|
// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
|
|
// CHECK19-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
|
|
// CHECK19-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
|
|
// CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
|
|
// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
|
|
// CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
|
|
// CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
|
|
// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
|
|
// CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
|
|
// CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4
|
|
// CHECK19-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
|
|
// CHECK19-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
|
|
// CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK19-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2
|
|
// CHECK19-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK19-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4
|
|
// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4
|
|
// CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP66]], align 4
|
|
// CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4
|
|
// CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4
|
|
// CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK19-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK19: omp_offload.failed9:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK19: omp_offload.cont10:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
|
|
// CHECK19-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK19-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
|
|
// CHECK19-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK19: omp_if.then13:
|
|
// CHECK19-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK19-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
|
|
// CHECK19-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK19-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
|
|
// CHECK19-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
|
|
// CHECK19-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false)
|
|
// CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4
|
|
// CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4
|
|
// CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP92]], align 4
|
|
// CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
|
|
// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
|
|
// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
|
|
// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP97]], align 4
|
|
// CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4
|
|
// CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4
|
|
// CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP102]], align 4
|
|
// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float**
|
|
// CHECK19-NEXT: store float* [[VLA]], float** [[TMP104]], align 4
|
|
// CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK19-NEXT: store float* [[VLA]], float** [[TMP106]], align 4
|
|
// CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK19-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4
|
|
// CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP108]], align 4
|
|
// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK19-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]**
|
|
// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4
|
|
// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
|
|
// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK19-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
|
|
// CHECK19-NEXT: store i32 5, i32* [[TMP115]], align 4
|
|
// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK19-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
|
|
// CHECK19-NEXT: store i32 5, i32* [[TMP117]], align 4
|
|
// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP118]], align 4
|
|
// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4
|
|
// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK19-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4
|
|
// CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP123]], align 4
|
|
// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK19-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double**
|
|
// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4
|
|
// CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK19-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK19-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4
|
|
// CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK19-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4
|
|
// CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP129]], align 4
|
|
// CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK19-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT**
|
|
// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4
|
|
// CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK19-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4
|
|
// CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP134]], align 4
|
|
// CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK19-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4
|
|
// CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK19-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4
|
|
// CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP139]], align 4
|
|
// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK19-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK19: omp_offload.failed17:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK19: omp_offload.cont18:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK19: omp_if.else19:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK19: omp_if.end20:
|
|
// CHECK19-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP146]])
|
|
// CHECK19-NEXT: ret i32 [[TMP145]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK19-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK19: .cancel.exit:
|
|
// CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK19: .cancel.continue:
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK19: .cancel.exit2:
|
|
// CHECK19-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK19: .cancel.continue3:
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK19: cancel.cont:
|
|
// CHECK19-NEXT: ret void
|
|
// CHECK19: cancel.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK19: omp.dispatch.cond:
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK19: omp.dispatch.body:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK19-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK19-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK19: omp.dispatch.inc:
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK19: omp.dispatch.end:
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK19: .omp.linear.pu:
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8
|
|
// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK19: .omp.linear.pu.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK19: .omp.linear.pu:
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK19: .omp.linear.pu.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
|
|
// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
|
|
// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
|
|
// CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK19: omp_offload.failed.i:
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK19: .omp_outlined..3.exit:
|
|
// CHECK19-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK19: omp.dispatch.cond:
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK19: omp.dispatch.body:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK19: omp.dispatch.inc:
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK19: omp.dispatch.end:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false)
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
|
|
// CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4
|
|
// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4
|
|
// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4
|
|
// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]]
|
|
// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]]
|
|
// CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK19-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK19-SAME: () #[[ATTR6]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK20-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK20-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK20-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP6]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK20-NEXT: store i64 [[CALL]], i64* [[K]], align 8
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP7]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP8]], i64* [[K]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: store i32 12, i32* [[LIN]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP11]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP13]], i32* [[A_CASTED2]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED2]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP16]], align 4
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP18]], align 4
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP21]], align 4
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP23]], align 4
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP26]], align 4
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP28]], align 4
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP29]], align 4
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4
|
|
// CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4
|
|
// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP37:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4
|
|
// CHECK20-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
|
|
// CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates*
|
|
// CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 4
|
|
// CHECK20-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8*
|
|
// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i32 12, i1 false)
|
|
// CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon*
|
|
// CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i64]* [[TMP46]] to i8*
|
|
// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false)
|
|
// CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP49:%.*]] = bitcast [3 x i8*]* [[TMP48]] to i8*
|
|
// CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP30]] to i8*
|
|
// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 [[TMP50]], i32 12, i1 false)
|
|
// CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP52:%.*]] = bitcast [3 x i8*]* [[TMP51]] to i8*
|
|
// CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP31]] to i8*
|
|
// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP52]], i8* align 4 [[TMP53]], i32 12, i1 false)
|
|
// CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 4
|
|
// CHECK20-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP38]])
|
|
// CHECK20-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP57]], i32* [[A_CASTED3]], align 4
|
|
// CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[A_CASTED3]], align 4
|
|
// CHECK20-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP59]], i16* [[CONV5]], align 2
|
|
// CHECK20-NEXT: [[TMP60:%.*]] = load i32, i32* [[AA_CASTED4]], align 4
|
|
// CHECK20-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP61]], 10
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK20: omp_if.then:
|
|
// CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP63]], align 4
|
|
// CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP65]], align 4
|
|
// CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP66]], align 4
|
|
// CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP68]], align 4
|
|
// CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP60]], i32* [[TMP70]], align 4
|
|
// CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP71]], align 4
|
|
// CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP74:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146.region_id, i32 2, i8** [[TMP72]], i8** [[TMP73]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK20-NEXT: [[TMP75:%.*]] = icmp ne i32 [[TMP74]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP75]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK20: omp_offload.failed9:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK20: omp_offload.cont10:
|
|
// CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK20: omp_if.else:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146(i32 [[TMP58]], i32 [[TMP60]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK20: omp_if.end:
|
|
// CHECK20-NEXT: [[TMP76:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP77]], i32* [[A_CASTED11]], align 4
|
|
// CHECK20-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED11]], align 4
|
|
// CHECK20-NEXT: [[TMP79:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP79]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP81]], 20
|
|
// CHECK20-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]]
|
|
// CHECK20: omp_if.then13:
|
|
// CHECK20-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK20-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64
|
|
// CHECK20-NEXT: [[TMP84:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK20-NEXT: [[TMP85:%.*]] = mul nuw i32 [[TMP84]], 8
|
|
// CHECK20-NEXT: [[TMP86:%.*]] = sext i32 [[TMP85]] to i64
|
|
// CHECK20-NEXT: [[TMP87:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP87]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false)
|
|
// CHECK20-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP89]], align 4
|
|
// CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP78]], i32* [[TMP91]], align 4
|
|
// CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP92]], align 4
|
|
// CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to [10 x float]**
|
|
// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP94]], align 4
|
|
// CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to [10 x float]**
|
|
// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP96]], align 4
|
|
// CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP97]], align 4
|
|
// CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP99]], align 4
|
|
// CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP101]], align 4
|
|
// CHECK20-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP102]], align 4
|
|
// CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to float**
|
|
// CHECK20-NEXT: store float* [[VLA]], float** [[TMP104]], align 4
|
|
// CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to float**
|
|
// CHECK20-NEXT: store float* [[VLA]], float** [[TMP106]], align 4
|
|
// CHECK20-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK20-NEXT: store i64 [[TMP83]], i64* [[TMP107]], align 4
|
|
// CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP108]], align 4
|
|
// CHECK20-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK20-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to [5 x [10 x double]]**
|
|
// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP110]], align 4
|
|
// CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to [5 x [10 x double]]**
|
|
// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP112]], align 4
|
|
// CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP113]], align 4
|
|
// CHECK20-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK20-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32*
|
|
// CHECK20-NEXT: store i32 5, i32* [[TMP115]], align 4
|
|
// CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK20-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32*
|
|
// CHECK20-NEXT: store i32 5, i32* [[TMP117]], align 4
|
|
// CHECK20-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP118]], align 4
|
|
// CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP120]], align 4
|
|
// CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK20-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP122]], align 4
|
|
// CHECK20-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP123]], align 4
|
|
// CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK20-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to double**
|
|
// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP125]], align 4
|
|
// CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK20-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to double**
|
|
// CHECK20-NEXT: store double* [[VLA1]], double** [[TMP127]], align 4
|
|
// CHECK20-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK20-NEXT: store i64 [[TMP86]], i64* [[TMP128]], align 4
|
|
// CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP129]], align 4
|
|
// CHECK20-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK20-NEXT: [[TMP131:%.*]] = bitcast i8** [[TMP130]] to %struct.TT**
|
|
// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP131]], align 4
|
|
// CHECK20-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK20-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to %struct.TT**
|
|
// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP133]], align 4
|
|
// CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP134]], align 4
|
|
// CHECK20-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK20-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP136]], align 4
|
|
// CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK20-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP80]], i32* [[TMP138]], align 4
|
|
// CHECK20-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP139]], align 4
|
|
// CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170.region_id, i32 10, i8** [[TMP140]], i8** [[TMP141]], i64* [[TMP142]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK20-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
|
|
// CHECK20: omp_offload.failed17:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]]
|
|
// CHECK20: omp_offload.cont18:
|
|
// CHECK20-NEXT: br label [[OMP_IF_END20:%.*]]
|
|
// CHECK20: omp_if.else19:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170(i32 [[TMP78]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP80]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_IF_END20]]
|
|
// CHECK20: omp_if.end20:
|
|
// CHECK20-NEXT: [[TMP145:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP146:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP146]])
|
|
// CHECK20-NEXT: ret i32 [[TMP145]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK20-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK20: .cancel.exit:
|
|
// CHECK20-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK20: .cancel.continue:
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK20: .cancel.exit2:
|
|
// CHECK20-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK20: .cancel.continue3:
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK20-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK20: cancel.cont:
|
|
// CHECK20-NEXT: ret void
|
|
// CHECK20: cancel.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK20-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK20-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK20-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK20: omp.dispatch.cond:
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]])
|
|
// CHECK20-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK20: omp.dispatch.body:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK20-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK20-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK20-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK20: omp.dispatch.inc:
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK20: omp.dispatch.end:
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK20: .omp.linear.pu:
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[K1]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP15]], i64* [[TMP0]], align 8
|
|
// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK20: .omp.linear.pu.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK20-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK20-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK20-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK20-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK20-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK20-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK20-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK20-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK20-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK20-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK20-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK20-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK20-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK20-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK20: .omp.linear.pu:
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK20: .omp.linear.pu.done:
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4
|
|
// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4
|
|
// CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4
|
|
// CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4
|
|
// CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4
|
|
// CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4
|
|
// CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4
|
|
// CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4
|
|
// CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4
|
|
// CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
|
|
// CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
|
|
// CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
|
|
// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4
|
|
// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4
|
|
// CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8*
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
|
|
// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)*
|
|
// CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]]
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK20: omp_offload.failed.i:
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = load i16, i16* [[TMP16]], align 2
|
|
// CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP27]], i16* [[CONV_I]], align 2, !noalias !25
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[TMP23]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP29]], i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP24]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP31]], i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138(i32 [[TMP28]], i32 [[TMP30]], i32 [[TMP32]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK20: .omp_outlined..3.exit:
|
|
// CHECK20-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK20-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK20-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK20: omp.dispatch.cond:
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK20-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK20: omp.dispatch.body:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK20-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK20-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK20-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK20-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK20-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK20-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK20-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK20-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK20-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK20-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK20-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK20-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK20-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK20-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK20-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK20-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK20-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK20-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK20-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK20-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK20-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK20: omp.dispatch.inc:
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK20-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK20-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK20-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK20: omp.dispatch.end:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4
|
|
// CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave()
|
|
// CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK20: omp_if.then:
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8*
|
|
// CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false)
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1**
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double**
|
|
// CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32*
|
|
// CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32*
|
|
// CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16**
|
|
// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4
|
|
// CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16**
|
|
// CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4
|
|
// CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4
|
|
// CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4
|
|
// CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK20: omp_if.else:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK20: omp_if.end:
|
|
// CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]]
|
|
// CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
|
|
// CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32
|
|
// CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4
|
|
// CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]]
|
|
// CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
|
|
// CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]])
|
|
// CHECK20-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK20: omp_if.then:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
|
|
// CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4
|
|
// CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK20: omp_if.else:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK20: omp_if.end:
|
|
// CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
|
|
// CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 0, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i16 0, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK20: omp_if.then:
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
|
|
// CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
|
|
// CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
|
|
// CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4
|
|
// CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
|
|
// CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
|
|
// CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK20: omp_offload.failed:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK20: omp_offload.cont:
|
|
// CHECK20-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK20: omp_if.else:
|
|
// CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]]
|
|
// CHECK20-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK20: omp_if.end:
|
|
// CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4
|
|
// CHECK20-NEXT: ret i32 [[TMP24]]
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK20-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK20-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK20-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK20-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK20-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK20-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK20-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK20-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK20-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK20-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK20-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK20-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK20-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK20-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK20: cond.true:
|
|
// CHECK20-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK20: cond.false:
|
|
// CHECK20-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: br label [[COND_END]]
|
|
// CHECK20: cond.end:
|
|
// CHECK20-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK20-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK20-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK20: omp.inner.for.cond:
|
|
// CHECK20-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK20-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK20-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK20: omp.inner.for.body:
|
|
// CHECK20-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK20-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK20-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK20-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK20-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK20-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK20-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK20-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK20: omp.body.continue:
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK20: omp.inner.for.inc:
|
|
// CHECK20-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK20-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK20-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK20: omp.inner.for.end:
|
|
// CHECK20-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK20: omp.loop.exit:
|
|
// CHECK20-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK20-SAME: () #[[ATTR6]] {
|
|
// CHECK20-NEXT: entry:
|
|
// CHECK20-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK20-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK25: cond.true:
|
|
// CHECK25-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK25: cond.false:
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: br label [[COND_END]]
|
|
// CHECK25: cond.end:
|
|
// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK25-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK25-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK25: .cancel.exit:
|
|
// CHECK25-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK25: .cancel.continue:
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK25-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK25: .cancel.exit2:
|
|
// CHECK25-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK25: .cancel.continue3:
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK25: omp.loop.exit:
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK25-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK25: cancel.cont:
|
|
// CHECK25-NEXT: ret void
|
|
// CHECK25: cancel.exit:
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK25-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK25-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK25-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK25-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK25-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK25: cond.true:
|
|
// CHECK25-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK25: cond.false:
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: br label [[COND_END]]
|
|
// CHECK25: cond.end:
|
|
// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK25-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK25-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK25-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK25-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK25-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK25-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK25-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK25-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK25-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK25-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK25-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK25-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK25-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK25: omp.loop.exit:
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK25-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK25-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK25: .omp.linear.pu:
|
|
// CHECK25-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK25-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK25-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK25: .omp.linear.pu.done:
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK25-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK25: cond.true:
|
|
// CHECK25-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK25: cond.false:
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: br label [[COND_END]]
|
|
// CHECK25: cond.end:
|
|
// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK25-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK25-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK25: omp.loop.exit:
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK25-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK25-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK25: omp.dispatch.cond:
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK25: cond.true:
|
|
// CHECK25-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK25: cond.false:
|
|
// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: br label [[COND_END]]
|
|
// CHECK25: cond.end:
|
|
// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK25-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK25: omp.dispatch.body:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK25-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK25-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK25-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK25-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK25-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK25-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK25-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK25-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK25-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK25-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK25-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK25-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK25-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK25-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK25-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK25-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK25-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK25-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK25-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK25-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK25-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK25-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK25-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK25-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK25-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK25: omp.dispatch.inc:
|
|
// CHECK25-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK25-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK25-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK25-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK25-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK25-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK25: omp.dispatch.end:
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK25: cond.true:
|
|
// CHECK25-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK25: cond.false:
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: br label [[COND_END]]
|
|
// CHECK25: cond.end:
|
|
// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK25-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK25-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK25-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK25-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK25-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK25-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK25-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK25-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK25-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK25-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK25: omp.loop.exit:
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK25-NEXT: entry:
|
|
// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK25-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK25-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK25-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK25: cond.true:
|
|
// CHECK25-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK25: cond.false:
|
|
// CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: br label [[COND_END]]
|
|
// CHECK25: cond.end:
|
|
// CHECK25-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK25-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK25-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK25: omp.inner.for.cond:
|
|
// CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK25: omp.inner.for.body:
|
|
// CHECK25-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK25-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK25-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK25-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK25-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK25-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK25-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK25-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK25-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK25-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK25: omp.body.continue:
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK25: omp.inner.for.inc:
|
|
// CHECK25-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK25-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK25: omp.inner.for.end:
|
|
// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK25: omp.loop.exit:
|
|
// CHECK25-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK25-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK26-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK26: cond.true:
|
|
// CHECK26-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK26: cond.false:
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: br label [[COND_END]]
|
|
// CHECK26: cond.end:
|
|
// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK26-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK26-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK26-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK26: .cancel.exit:
|
|
// CHECK26-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK26: .cancel.continue:
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK26-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK26: .cancel.exit2:
|
|
// CHECK26-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK26: .cancel.continue3:
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK26: omp.loop.exit:
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK26-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK26: cancel.cont:
|
|
// CHECK26-NEXT: ret void
|
|
// CHECK26: cancel.exit:
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK26-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK26-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[LIN4:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[A5:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK26-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK26-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK26-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK26: cond.true:
|
|
// CHECK26-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK26: cond.false:
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: br label [[COND_END]]
|
|
// CHECK26: cond.end:
|
|
// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK26-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK26-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK26-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK26-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4
|
|
// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4
|
|
// CHECK26-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK26-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK26-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]]
|
|
// CHECK26-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32
|
|
// CHECK26-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4
|
|
// CHECK26-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK26-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK26-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1
|
|
// CHECK26-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK26: omp.loop.exit:
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK26-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK26-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK26: .omp.linear.pu:
|
|
// CHECK26-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN4]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP20]], i32* [[CONV1]], align 4
|
|
// CHECK26-NEXT: [[TMP21:%.*]] = load i32, i32* [[A5]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP21]], i32* [[CONV2]], align 4
|
|
// CHECK26-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK26: .omp.linear.pu.done:
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK26-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK26: cond.true:
|
|
// CHECK26-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK26: cond.false:
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: br label [[COND_END]]
|
|
// CHECK26: cond.end:
|
|
// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK26-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK26-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
|
|
// CHECK26-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK26: omp.loop.exit:
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK26-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8
|
|
// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8
|
|
// CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
|
|
// CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8
|
|
// CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
|
|
// CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8
|
|
// CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32*
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK26-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK26: omp.dispatch.cond:
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK26: cond.true:
|
|
// CHECK26-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK26: cond.false:
|
|
// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: br label [[COND_END]]
|
|
// CHECK26: cond.end:
|
|
// CHECK26-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK26-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK26-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK26: omp.dispatch.body:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK26-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK26-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK26-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1
|
|
// CHECK26-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
|
|
// CHECK26-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
|
|
// CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
|
|
// CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4
|
|
// CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
|
|
// CHECK26-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4
|
|
// CHECK26-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
|
|
// CHECK26-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
|
|
// CHECK26-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4
|
|
// CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
|
|
// CHECK26-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
|
|
// CHECK26-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8
|
|
// CHECK26-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK26-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8
|
|
// CHECK26-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK26-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]]
|
|
// CHECK26-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
|
|
// CHECK26-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8
|
|
// CHECK26-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK26-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8
|
|
// CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK26-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8
|
|
// CHECK26-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD22]], i64* [[X]], align 8
|
|
// CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK26-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8
|
|
// CHECK26-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK26-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
|
|
// CHECK26-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
|
|
// CHECK26-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK26: omp.dispatch.inc:
|
|
// CHECK26-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK26-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK26-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK26-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK26-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK26-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK26: omp.dispatch.end:
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1
|
|
// CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
|
|
// CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
|
|
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK26: cond.true:
|
|
// CHECK26-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK26: cond.false:
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: br label [[COND_END]]
|
|
// CHECK26: cond.end:
|
|
// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK26-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK26-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK26-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK26-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00
|
|
// CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8
|
|
// CHECK26-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8
|
|
// CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK26-NEXT: store double [[INC]], double* [[A5]], align 8
|
|
// CHECK26-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK26-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]]
|
|
// CHECK26-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
|
|
// CHECK26-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK26: omp.loop.exit:
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
|
|
// CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
|
|
// CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
|
|
// CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK26-NEXT: entry:
|
|
// CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK26-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8
|
|
// CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
|
|
// CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
|
|
// CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
|
|
// CHECK26-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK26-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK26-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK26: cond.true:
|
|
// CHECK26-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK26: cond.false:
|
|
// CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: br label [[COND_END]]
|
|
// CHECK26: cond.end:
|
|
// CHECK26-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK26-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK26-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK26: omp.inner.for.cond:
|
|
// CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK26-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK26-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK26: omp.inner.for.body:
|
|
// CHECK26-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK26-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK26-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK26-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4
|
|
// CHECK26-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2
|
|
// CHECK26-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK26-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK26-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2
|
|
// CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
|
|
// CHECK26-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK26-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK26-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK26: omp.body.continue:
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK26: omp.inner.for.inc:
|
|
// CHECK26-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK26-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK26-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK26: omp.inner.for.end:
|
|
// CHECK26-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK26: omp.loop.exit:
|
|
// CHECK26-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK26-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK27-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK27: cond.true:
|
|
// CHECK27-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK27: cond.false:
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: br label [[COND_END]]
|
|
// CHECK27: cond.end:
|
|
// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK27-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK27-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK27: .cancel.exit:
|
|
// CHECK27-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK27: .cancel.continue:
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK27-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK27: .cancel.exit2:
|
|
// CHECK27-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK27: .cancel.continue3:
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK27: omp.loop.exit:
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK27-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK27: cancel.cont:
|
|
// CHECK27-NEXT: ret void
|
|
// CHECK27: cancel.exit:
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK27-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK27-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK27-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK27-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK27-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK27: cond.true:
|
|
// CHECK27-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK27: cond.false:
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: br label [[COND_END]]
|
|
// CHECK27: cond.end:
|
|
// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK27-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK27-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK27-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK27-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK27-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK27-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK27-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK27-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK27-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK27-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK27-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK27-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK27-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK27: omp.loop.exit:
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK27-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK27-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK27: .omp.linear.pu:
|
|
// CHECK27-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK27: .omp.linear.pu.done:
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK27-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK27: cond.true:
|
|
// CHECK27-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK27: cond.false:
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: br label [[COND_END]]
|
|
// CHECK27: cond.end:
|
|
// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK27-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK27-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK27: omp.loop.exit:
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK27-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK27: omp.dispatch.cond:
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK27: cond.true:
|
|
// CHECK27-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK27: cond.false:
|
|
// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: br label [[COND_END]]
|
|
// CHECK27: cond.end:
|
|
// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK27-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK27: omp.dispatch.body:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK27-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK27-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK27-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK27-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK27-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK27-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK27-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK27-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK27-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK27-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK27-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK27-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK27-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK27-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK27-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK27-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK27-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK27-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK27-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK27-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK27-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK27-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK27-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK27-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK27-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK27-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK27-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK27-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK27-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK27: omp.dispatch.inc:
|
|
// CHECK27-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK27-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK27-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK27-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK27-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK27-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK27: omp.dispatch.end:
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK27: cond.true:
|
|
// CHECK27-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK27: cond.false:
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: br label [[COND_END]]
|
|
// CHECK27: cond.end:
|
|
// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK27-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK27-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK27-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK27-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK27-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK27-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK27-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK27-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK27-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK27-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK27: omp.loop.exit:
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK27-NEXT: entry:
|
|
// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK27-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK27-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK27-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK27-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK27: cond.true:
|
|
// CHECK27-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK27: cond.false:
|
|
// CHECK27-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: br label [[COND_END]]
|
|
// CHECK27: cond.end:
|
|
// CHECK27-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK27-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK27-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK27: omp.inner.for.cond:
|
|
// CHECK27-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK27: omp.inner.for.body:
|
|
// CHECK27-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK27-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK27-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK27-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK27-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK27-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK27-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK27-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK27: omp.body.continue:
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK27: omp.inner.for.inc:
|
|
// CHECK27-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK27-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK27: omp.inner.for.end:
|
|
// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK27: omp.loop.exit:
|
|
// CHECK27-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK27-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK28-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK28: cond.true:
|
|
// CHECK28-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK28: cond.false:
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: br label [[COND_END]]
|
|
// CHECK28: cond.end:
|
|
// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK28-NEXT: store i32 [[ADD]], i32* [[I]], align 4
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK28-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK28: .cancel.exit:
|
|
// CHECK28-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK28: .cancel.continue:
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK28-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK28: .cancel.exit2:
|
|
// CHECK28-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK28: .cancel.continue3:
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK28: omp.loop.exit:
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK28-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK28: cancel.cont:
|
|
// CHECK28-NEXT: ret void
|
|
// CHECK28: cancel.exit:
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK28-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l138
|
|
// CHECK28-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK28-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK28-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK28-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK28: cond.true:
|
|
// CHECK28-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK28: cond.false:
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: br label [[COND_END]]
|
|
// CHECK28: cond.end:
|
|
// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK28-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4
|
|
// CHECK28-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK28-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]]
|
|
// CHECK28-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK28-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4
|
|
// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4
|
|
// CHECK28-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8
|
|
// CHECK28-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK28-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]]
|
|
// CHECK28-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32
|
|
// CHECK28-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4
|
|
// CHECK28-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK28-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
|
|
// CHECK28-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK28: omp.loop.exit:
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK28-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK28-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK28: .omp.linear.pu:
|
|
// CHECK28-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN2]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP20]], i32* [[LIN_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP21:%.*]] = load i32, i32* [[A3]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP21]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK28: .omp.linear.pu.done:
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK28-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l146
|
|
// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK28: cond.true:
|
|
// CHECK28-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK28: cond.false:
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: br label [[COND_END]]
|
|
// CHECK28: cond.end:
|
|
// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK28-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1
|
|
// CHECK28-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK28: omp.loop.exit:
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l170
|
|
// CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4
|
|
// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4
|
|
// CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
|
|
// CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4
|
|
// CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
|
|
// CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4
|
|
// CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK28-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK28: omp.dispatch.cond:
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK28: cond.true:
|
|
// CHECK28-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK28: cond.false:
|
|
// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: br label [[COND_END]]
|
|
// CHECK28: cond.end:
|
|
// CHECK28-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK28-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK28-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK28: omp.dispatch.body:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK28-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK28-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK28-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK28-NEXT: store i8 [[CONV]], i8* [[IT]], align 1
|
|
// CHECK28-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
|
|
// CHECK28-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4
|
|
// CHECK28-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK28-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK28-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK28-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4
|
|
// CHECK28-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
|
|
// CHECK28-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4
|
|
// CHECK28-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK28-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK28-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK28-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4
|
|
// CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
|
|
// CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK28-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8
|
|
// CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8
|
|
// CHECK28-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK28-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]]
|
|
// CHECK28-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3
|
|
// CHECK28-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8
|
|
// CHECK28-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK28-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8
|
|
// CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
|
|
// CHECK28-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4
|
|
// CHECK28-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD20]], i64* [[X]], align 4
|
|
// CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
|
|
// CHECK28-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4
|
|
// CHECK28-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK28-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK28-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK28-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK28: omp.dispatch.inc:
|
|
// CHECK28-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK28-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK28-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4
|
|
// CHECK28-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4
|
|
// CHECK28-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK28-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK28: omp.dispatch.end:
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l224
|
|
// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1
|
|
// CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
|
|
// CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
|
|
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l242
|
|
// CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
|
|
// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK28: cond.true:
|
|
// CHECK28-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK28: cond.false:
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: br label [[COND_END]]
|
|
// CHECK28: cond.end:
|
|
// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK28-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK28-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK28-NEXT: store i64 [[SUB]], i64* [[IT]], align 8
|
|
// CHECK28-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4
|
|
// CHECK28-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
|
|
// CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4
|
|
// CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK28-NEXT: store double [[INC]], double* [[A4]], align 4
|
|
// CHECK28-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK28-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]]
|
|
// CHECK28-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
|
|
// CHECK28-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK28: omp.loop.exit:
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l207
|
|
// CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
|
|
// CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
|
|
// CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK28-NEXT: entry:
|
|
// CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
|
|
// CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK28-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK28-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4
|
|
// CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
|
|
// CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
|
|
// CHECK28-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8
|
|
// CHECK28-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK28-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK28-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK28: cond.true:
|
|
// CHECK28-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK28: cond.false:
|
|
// CHECK28-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: br label [[COND_END]]
|
|
// CHECK28: cond.end:
|
|
// CHECK28-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK28-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8
|
|
// CHECK28-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK28: omp.inner.for.cond:
|
|
// CHECK28-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8
|
|
// CHECK28-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK28-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK28: omp.inner.for.body:
|
|
// CHECK28-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK28-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK28-NEXT: store i64 [[ADD]], i64* [[I]], align 8
|
|
// CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4
|
|
// CHECK28-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK28-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK28-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2
|
|
// CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
|
|
// CHECK28-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
|
|
// CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK28-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
|
|
// CHECK28-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK28: omp.body.continue:
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK28: omp.inner.for.inc:
|
|
// CHECK28-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK28-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8
|
|
// CHECK28-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK28: omp.inner.for.end:
|
|
// CHECK28-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK28: omp.loop.exit:
|
|
// CHECK28-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK28-NEXT: ret void
|
|
//
|