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Piotr Sobczak 265e94e657 [AMDGPU] Extend buffer intrinsics with swizzling 
Summary:
Extend cachepolicy operand in the new VMEM buffer intrinsics
to supply information whether the buffer data is swizzled.
Also, propagate this information to MIR.

Intrinsics updated:
int_amdgcn_raw_buffer_load
int_amdgcn_raw_buffer_load_format
int_amdgcn_raw_buffer_store
int_amdgcn_raw_buffer_store_format
int_amdgcn_raw_tbuffer_load
int_amdgcn_raw_tbuffer_store
int_amdgcn_struct_buffer_load
int_amdgcn_struct_buffer_load_format
int_amdgcn_struct_buffer_store
int_amdgcn_struct_buffer_store_format
int_amdgcn_struct_tbuffer_load
int_amdgcn_struct_tbuffer_store

Furthermore, disable merging of VMEM buffer instructions
in SI Load/Store optimizer, if the "swizzled" bit on the instruction
is on.

The default value of the bit is 0, meaning that data in buffer
is linear and buffer instructions can be merged.

There is no difference in the generated code with this commit.
However, in the future it will be expected that front-ends
use buffer intrinsics with correct "swizzled" bit set.

Reviewers: arsenm, nhaehnle, tpr

Reviewed By: nhaehnle

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68200

llvm-svn: 373491
 		2019-10-02 17:22:36 +00:00
..
AArch64 [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsic 2019-10-02 13:09:54 +00:00
AMDGPU [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
ARC
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ARM Add a missing pass in ARM O3 pipeline 2019-10-01 18:53:54 +00:00
AVR
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BPF [BPF] Generate array dimension size properly for zero-size elements 2019-09-24 22:38:43 +00:00
Generic Revert "Reland "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."" 2019-09-10 10:39:09 +00:00
Hexagon [ModuloSchedule] Peel out prologs and epilogs, generate actual code 2019-10-02 12:46:44 +00:00
Inputs
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Lanai [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
MIR [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
MSP430 [MSP430] Allow msp430_intrcc functions to not have interrupt attribute. 2019-09-25 18:58:07 +00:00
Mips Add an operand to memory intrinsics to denote the "tail" marker. 2019-09-28 05:33:21 +00:00
NVPTX
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PowerPC [PowerPC] make tests immune to improved undef handling 2019-09-28 13:34:53 +00:00
RISCV [TargetLowering] Simplify expansion of S{ADD,SUB}O 2019-09-30 07:58:50 +00:00
SPARC [test] Fix tests when run on windows after SVN r369426. NFC. 2019-08-20 20:58:02 +00:00
SystemZ [SystemZ] Add SystemZPostRewrite in addPostRegAlloc() instead at -O0. 2019-09-30 07:29:54 +00:00
Thumb [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Thumb2 [ARM] Identity shuffles are legal 2019-10-02 11:40:51 +00:00
WebAssembly [WebAssembly] Make sure EH pads are preferred in sorting 2019-10-01 06:53:28 +00:00
WinCFGuard
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WinEH [Windows] Replace TrapUnreachable with an int3 insertion pass 2019-09-09 23:04:25 +00:00
X86 Reapply r373431 "Switch lowering: omit range check for bit tests when default is unreachable (PR43129)" 2019-10-02 14:35:06 +00:00
XCore
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