llvm-project/llvm/test/CodeGen/SPARC
Vedant Kumar ee4bfcaa5a [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
Setting the right SDLoc on a newly-created zextload fixes a line table
bug which resulted in non-linear stepping behavior.

Several backend tests contained CHECK lines which relied on the IROrder
inherited from the wrong SDLoc. This patch breaks that dependence where
feasbile and regenerates test cases where not.

In some cases, changing a node's IROrder may alter register allocation
and spill behavior. This can affect performance. I have chosen not to
prevent this by applying a "known good" IROrder to SDLocs, as this may
hide a more general bug in the scheduler, or cause regressions on other
test inputs.

rdar://33755881, Part of: llvm.org/PR37262

Differential Revision: https://reviews.llvm.org/D45995

llvm-svn: 331300
2018-05-01 19:26:15 +00:00
..
32abi.ll [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N) 2018-05-01 19:26:15 +00:00
64abi.ll [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N) 2018-05-01 19:26:15 +00:00
64bit.ll
64cond.ll [Sparc] Return true in enableMultipleCopyHints(). 2018-02-24 08:24:31 +00:00
64spill.ll
2006-01-22-BitConvertLegalize.ll
2007-05-09-JumpTables.ll
2007-07-05-LiveIntervalAssert.ll
2008-10-10-InlineAsmMemoryOperand.ll
2008-10-10-InlineAsmRegOperand.ll
2009-08-28-PIC.ll
2009-08-28-WeakLinkage.ll
2011-01-11-CC.ll
2011-01-11-Call.ll
2011-01-11-FrameAddr.ll
2011-01-19-DelaySlot.ll
2011-01-21-ByValArgs.ll
2011-01-22-SRet.ll
2011-12-03-TailDuplication.ll
2012-05-01-LowerArguments.ll
2013-05-17-CallFrame.ll
DbgValueOtherTargets.test
LeonCASAInstructionUT.ll Add support for Myriad ma2x8x series of CPUs 2017-10-02 18:50:48 +00:00
LeonDetectRoundChangePassUT.ll
LeonFixAllFDIVSQRTPassUT.ll [Sparc] Remove execute permissions from non-executable text files 2017-05-17 11:05:20 +00:00
LeonInsertNOPLoadPassUT.ll [Sparc] Remove execute permissions from non-executable text files 2017-05-17 11:05:20 +00:00
LeonItinerariesUT.ll [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
LeonSMACUMACInstructionUT.ll [Sparc] Remove execute permissions from non-executable text files 2017-05-17 11:05:20 +00:00
analyze-branch.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
atomics.ll [Sparc] Use synthetic instruction clr to zero register instead of sethi 2018-04-20 07:47:12 +00:00
basictest.ll
blockaddr.ll
constpool.ll
constructor.ll [Solaris] emit .init_array instead of .ctors on Solaris (Sparc/x86) 2017-06-21 20:36:32 +00:00
ctpop.ll
disable-fsmuld-fmuls.ll [SPARC] Clean up the support for disabling fsmuld and fmuls instructions. 2017-07-20 20:09:11 +00:00
empty-functions.ll Don't emit CFI instructions at the end of a function 2017-04-24 18:45:59 +00:00
exception.ll
fail-alloca-align.ll
float-constants.ll
float.ll Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion 2017-12-11 22:25:04 +00:00
fp128.ll
func-addr.ll
globals.ll
imm.ll [Sparc] Use synthetic instruction clr to zero register instead of sethi 2018-04-20 07:47:12 +00:00
inlineasm-v9.ll [SPARC] Support 'f' and 'e' inline asm constraints. 2017-05-12 15:59:10 +00:00
inlineasm.ll [Sparc] Use synthetic instruction clr to zero register instead of sethi 2018-04-20 07:47:12 +00:00
leafproc.ll
lit.local.cfg
mature-mc-support.ll [LLC] Add an inline assembly diagnostics handler. 2017-02-03 11:14:39 +00:00
missing-sret.ll
missinglabel.ll
mult-alt-generic-sparc.ll
multiple-div.ll
obj-relocs.ll
parts.ll
private.ll
register-clobber.ll Check for register clobbers when merging a vreg live range with a 2017-01-13 19:08:36 +00:00
rem.ll
reserved-regs.ll [Sparc] Check register use with isPhysRegUsed() instead of reg_nodbg_empty() 2017-03-08 15:23:10 +00:00
select-mask.ll
setjmp.ll
sjlj.ll [Sparc] Remove execute permissions from non-executable text files 2017-05-17 11:05:20 +00:00
soft-float.ll
soft-mul-div.ll [Sparc] Added software multiplication/division feature 2017-07-18 19:08:38 +00:00
spill.ll
spillsize.ll
sret-secondary.ll
stack-align.ll [Sparc] Account for bias in stack readjustment 2018-01-29 12:10:32 +00:00
stack-protector.ll
thread-pointer.ll
tls.ll [Sparc] Include __tls_get_addr in symbol table for TLS calls to it 2018-02-21 15:25:26 +00:00
trap.ll
varargs.ll
vector-call.ll
vector-extract-elt.ll [Sparc] Use synthetic instruction clr to zero register instead of sethi 2018-04-20 07:47:12 +00:00
zerostructcall.ll