forked from OSchip/llvm-project
122 lines
5.0 KiB
LLVM
122 lines
5.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; GCN-LABEL: {{^}}test_fmax3_olt_0_f32:
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; GCN: buffer_load_dword [[REGC:v[0-9]+]]
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; GCN: buffer_load_dword [[REGB:v[0-9]+]]
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; GCN: buffer_load_dword [[REGA:v[0-9]+]]
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; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define amdgpu_kernel void @test_fmax3_olt_0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
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%a = load volatile float, float addrspace(1)* %aptr, align 4
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%b = load volatile float, float addrspace(1)* %bptr, align 4
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%c = load volatile float, float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.maxnum.f32(float %a, float %b)
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%f1 = call float @llvm.maxnum.f32(float %f0, float %c)
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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; Commute operand of second fmax
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; GCN-LABEL: {{^}}test_fmax3_olt_1_f32:
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; GCN: buffer_load_dword [[REGB:v[0-9]+]]
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; GCN: buffer_load_dword [[REGA:v[0-9]+]]
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; GCN: buffer_load_dword [[REGC:v[0-9]+]]
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; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define amdgpu_kernel void @test_fmax3_olt_1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
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%a = load volatile float, float addrspace(1)* %aptr, align 4
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%b = load volatile float, float addrspace(1)* %bptr, align 4
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%c = load volatile float, float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.maxnum.f32(float %a, float %b)
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%f1 = call float @llvm.maxnum.f32(float %c, float %f0)
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_fmax3_olt_0_f16:
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; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
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; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]],
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; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
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; VI: v_max_f16_e32
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; VI: v_max_f16_e32 [[RESULT:v[0-9]+]],
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; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_short [[RESULT]],
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define amdgpu_kernel void @test_fmax3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
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%a = load volatile half, half addrspace(1)* %aptr, align 2
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%b = load volatile half, half addrspace(1)* %bptr, align 2
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%c = load volatile half, half addrspace(1)* %cptr, align 2
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%f0 = call half @llvm.maxnum.f16(half %a, half %b)
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%f1 = call half @llvm.maxnum.f16(half %f0, half %c)
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store half %f1, half addrspace(1)* %out, align 2
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ret void
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}
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; Commute operand of second fmax
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; GCN-LABEL: {{^}}test_fmax3_olt_1_f16:
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; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
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; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]],
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; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
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; VI: v_max_f16_e32
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; VI: v_max_f16_e32 [[RESULT:v[0-9]+]],
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; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_short [[RESULT]],
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define amdgpu_kernel void @test_fmax3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
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%a = load volatile half, half addrspace(1)* %aptr, align 2
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%b = load volatile half, half addrspace(1)* %bptr, align 2
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%c = load volatile half, half addrspace(1)* %cptr, align 2
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%f0 = call half @llvm.maxnum.f16(half %a, half %b)
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%f1 = call half @llvm.maxnum.f16(half %c, half %f0)
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store half %f1, half addrspace(1)* %out, align 2
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ret void
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}
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; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of max3
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; since there are no pack instructions for fmax3.
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; GCN-LABEL: {{^}}no_fmax3_v2f16:
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; SI: v_cvt_f16_f32_e32
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; SI: v_max_f32_e32
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; SI-NEXT: v_max_f32_e32
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; SI-NEXT: v_max3_f32
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; SI-NEXT: v_max3_f32
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; VI: v_max_f16_e32
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; VI-NEXT: v_max_f16_e32
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; VI-NEXT: v_max_f16_e32
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; VI-NEXT: v_max_f16_e32
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; VI-NEXT: v_max_f16_e32
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; VI-NEXT: v_max_f16_e32
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; GFX9: v_pk_max_f16
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; GFX9-NEXT: v_pk_max_f16
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; GFX9-NEXT: v_pk_max_f16
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define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
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entry:
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%max = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
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%max1 = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %max)
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%res = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %max1, <2 x half> %d)
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ret <2 x half> %res
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.maxnum.f32(float, float) #1
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declare half @llvm.maxnum.f16(half, half) #1
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declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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