forked from OSchip/llvm-project
176 lines
8.5 KiB
TableGen
176 lines
8.5 KiB
TableGen
//===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Record that INSN performs a 64-bit version of unary operator OPERATOR
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// in which the operand is sign-extended from 32 to 64 bits.
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multiclass SXU<SDPatternOperator operator, Instruction insn> {
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def : Pat<(operator (sext (i32 GR32:$src))),
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(insn GR32:$src)>;
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def : Pat<(operator (sext_inreg GR64:$src, i32)),
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(insn (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
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}
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// Record that INSN performs a 64-bit version of binary operator OPERATOR
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// in which the first operand has class CLS and which the second operand
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// is sign-extended from a 32-bit register.
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multiclass SXB<SDPatternOperator operator, RegisterOperand cls,
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Instruction insn> {
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def : Pat<(operator cls:$src1, (sext GR32:$src2)),
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(insn cls:$src1, GR32:$src2)>;
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def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
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(insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
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}
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// Like SXB, but for zero extension.
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multiclass ZXB<SDPatternOperator operator, RegisterOperand cls,
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Instruction insn> {
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def : Pat<(operator cls:$src1, (zext GR32:$src2)),
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(insn cls:$src1, GR32:$src2)>;
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def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
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(insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
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}
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// Record that INSN performs a binary read-modify-write operation,
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// with LOAD, OPERATOR and STORE being the read, modify and write
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// respectively. MODE is the addressing mode and IMM is the type
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// of the second operand.
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class RMWI<SDPatternOperator load, SDPatternOperator operator,
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SDPatternOperator store, AddressingMode mode,
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PatFrag imm, Instruction insn>
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: Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
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(insn mode:$addr, (UIMM8 imm:$src))>;
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// Record that INSN performs binary operation OPERATION on a byte
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// memory location. IMM is the type of the second operand.
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multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
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Instruction insn> {
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def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
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def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
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}
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// Record that INSN performs insertion TYPE into a register of class CLS.
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// The inserted operand is loaded using LOAD from an address of mode MODE.
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multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
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SDPatternOperator load, AddressingMode mode> {
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def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
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cls:$src1, (load mode:$src2)),
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(insn cls:$src1, mode:$src2)>;
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def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
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(load mode:$src2), cls:$src1),
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(insn cls:$src1, mode:$src2)>;
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}
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// INSN stores the low 32 bits of a GPR to a memory with addressing mode MODE.
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// Record that it is equivalent to using OPERATOR to store a GR64.
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class StoreGR64<Instruction insn, SDPatternOperator operator,
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AddressingMode mode>
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: Pat<(operator GR64:$R1, mode:$XBD2),
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(insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), mode:$XBD2)>;
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// INSN and INSNY are an RX/RXY pair of instructions that store the low
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// 32 bits of a GPR to memory. Record that they are equivalent to using
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// OPERATOR to store a GR64.
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multiclass StoreGR64Pair<Instruction insn, Instruction insny,
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SDPatternOperator operator> {
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def : StoreGR64<insn, operator, bdxaddr12pair>;
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def : StoreGR64<insny, operator, bdxaddr20pair>;
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}
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// INSN stores the low 32 bits of a GPR using PC-relative addressing.
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// Record that it is equivalent to using OPERATOR to store a GR64.
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class StoreGR64PC<Instruction insn, SDPatternOperator operator>
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: Pat<(operator GR64:$R1, pcrel32:$XBD2),
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(insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), pcrel32:$XBD2)> {
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// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
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// However, BDXs have two extra operands and are therefore 6 units more
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// complex.
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let AddedComplexity = 7;
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}
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// INSN and INSNINV conditionally store the low 32 bits of a GPR to memory,
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// with INSN storing when the condition is true and INSNINV storing when the
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// condition is false. Record that they are equivalent to a LOAD/select/STORE
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// sequence for GR64s.
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multiclass CondStores64<Instruction insn, Instruction insninv,
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SDPatternOperator store, SDPatternOperator load,
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AddressingMode mode> {
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def : Pat<(store (z_select_ccmask GR64:$new, (load mode:$addr),
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imm32zx4:$valid, imm32zx4:$cc),
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mode:$addr),
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(insn (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
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imm32zx4:$valid, imm32zx4:$cc)>;
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def : Pat<(store (z_select_ccmask (load mode:$addr), GR64:$new,
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imm32zx4:$valid, imm32zx4:$cc),
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mode:$addr),
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(insninv (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
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imm32zx4:$valid, imm32zx4:$cc)>;
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}
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// Try to use MVC instruction INSN for a load of type LOAD followed by a store
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// of the same size. VT is the type of the intermediate (legalized) value and
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// LENGTH is the number of bytes loaded by LOAD.
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multiclass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn,
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bits<5> length> {
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def : Pat<(mvc_store (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
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(insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
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}
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// Use NC-like instruction INSN for block_op operation OPERATOR.
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// The other operand is a load of type LOAD, which accesses LENGTH bytes.
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// VT is the intermediate legalized type in which the binary operation
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// is actually done.
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multiclass BinaryLoadStore<SDPatternOperator operator, SDPatternOperator load,
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ValueType vt, Instruction insn, bits<5> length> {
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def : Pat<(operator (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
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(insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
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}
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// A convenient way of generating all block peepholes for a particular
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// LOAD/VT/LENGTH combination.
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multiclass BlockLoadStore<SDPatternOperator load, ValueType vt,
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Instruction mvc, Instruction nc, Instruction oc,
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Instruction xc, bits<5> length> {
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defm : MVCLoadStore<load, vt, mvc, length>;
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defm : BinaryLoadStore<block_and1, load, vt, nc, length>;
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defm : BinaryLoadStore<block_and2, load, vt, nc, length>;
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defm : BinaryLoadStore<block_or1, load, vt, oc, length>;
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defm : BinaryLoadStore<block_or2, load, vt, oc, length>;
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defm : BinaryLoadStore<block_xor1, load, vt, xc, length>;
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defm : BinaryLoadStore<block_xor2, load, vt, xc, length>;
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}
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// Record that INSN is a LOAD AND TEST that can be used to compare
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// registers in CLS against zero. The instruction has separate R1 and R2
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// operands, but they must be the same when the instruction is used like this.
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multiclass CompareZeroFP<Instruction insn, RegisterOperand cls> {
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def : Pat<(z_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;
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// The sign of the zero makes no difference.
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def : Pat<(z_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg, cls:$reg)>;
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}
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// Use INSN for performing binary operation OPERATION of type VT
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// on registers of class CLS.
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class BinaryRRWithType<Instruction insn, RegisterOperand cls,
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SDPatternOperator operator, ValueType vt>
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: Pat<(vt (operator cls:$x, cls:$y)), (insn cls:$x, cls:$y)>;
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// Use INSN to perform conversion operation OPERATOR, with the input being
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// TR2 and the output being TR1. SUPPRESS is 4 to suppress inexact conditions
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// and 0 to allow them. MODE is the rounding mode to use.
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class FPConversion<Instruction insn, SDPatternOperator operator, TypedReg tr1,
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TypedReg tr2, bits<3> suppress, bits<4> mode>
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: Pat<(tr1.vt (operator (tr2.vt tr2.op:$vec))),
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(insn tr2.op:$vec, suppress, mode)>;
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// Use INSN to perform mininum/maximum operation OPERATOR on type TR.
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// FUNCTION is the type of minimum/maximum function to perform.
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class FPMinMax<Instruction insn, SDPatternOperator operator, TypedReg tr,
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bits<4> function>
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: Pat<(tr.vt (operator (tr.vt tr.op:$vec1), (tr.vt tr.op:$vec2))),
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(insn tr.op:$vec1, tr.op:$vec2, function)>;
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