Roger Ferrer Ibanez b621f04135 [RISCV] Diagnose invalid second input register operand when using %tprel_add ... RISCVMCCodeEmitter::expandAddTPRel asserts that the second operand must be x4/tp. As we are not currently checking this in the RISCVAsmParser, the assert is easy to trigger due to wrong assembly input. This patch does a late check of this constraint. An alternative could be using a singleton register class for x4/tp similar to the current one for sp. Unfortunately it does not result in a good diagnostic. Because add is an overloaded mnemonic, if no matching is possible, the diagnostic of the first failing alternative seems to be used as the diagnostic itself. This means that this case the %tprel_add is diagnosed as an invalid operand (because the real add instruction only has 3 operands). Differential Revision: https://reviews.llvm.org/D60528 llvm-svn: 358183		2019-04-11 15:13:12 +00:00
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CMakeLists.txt	…
LLVMBuild.txt	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVAsmParser.cpp	[RISCV] Diagnose invalid second input register operand when using %tprel_add	2019-04-11 15:13:12 +00:00