forked from OSchip/llvm-project
53 lines
2.8 KiB
TableGen
53 lines
2.8 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
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// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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// GISEL-OPT: GIM_SwitchOpcode
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// GISEL-OPT-NEXT: /*TargetOpcode::G_SHL*/
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// GISEL-OPT-NEXT: /*TargetOpcode::G_LSHR*/
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// GISEL-OPT-NEXT: // Label
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// GISEL-OPT: GIM_Try,
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// GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
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// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
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// GISEL-OPT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
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// GISEL-OPT: GIM_Try,
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// GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
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// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
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// GISEL-OPT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
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// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LSHR,
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// GISEL-NOOPT: // MIs[0] Operand 2
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// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
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// GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
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// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
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// GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
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// GISEL-NOOPT-NEXT: // MIs[1] Operand 0
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// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
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// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
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// GISEL-NOOPT-NEXT: // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllOnesV:{ *:[v4i16] }) => (VFOOONES:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0)
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def VFOOONES : I<(outs VecReg128:$dst), (ins VecReg128:$src0),
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[(set v4i32:$dst, (srl v4i32:$src0, (v4i16 immAllOnesV)))]
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>;
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// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SHL,
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// GISEL-NOOPT: // MIs[0] Operand 2
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// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
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// GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
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// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
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// GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
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// GISEL-NOOPT-NEXT: // MIs[1] Operand 0
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// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
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// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
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// GISEL-NOOPT-NEXT: // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllZerosV:{ *:[v4i16] }) => (VFOOZERO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0)
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def VFOOZERO : I<(outs VecReg128:$dst), (ins VecReg128:$src0),
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[(set v4i32:$dst, (shl v4i32:$src0, (v4i16 immAllZerosV)))]
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>;
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