forked from OSchip/llvm-project
39 lines
1.7 KiB
LLVM
39 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; Function Attrs: nounwind
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; CHECK: .func kernelgen_memcpy
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define ptx_device void @kernelgen_memcpy(i8* nocapture %dst) #0 {
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entry:
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br i1 undef, label %for.end, label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ]
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%scevgep9 = getelementptr i8, i8* %dst, i64 %index
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%scevgep910 = bitcast i8* %scevgep9 to <4 x i8>*
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store <4 x i8> undef, <4 x i8>* %scevgep910, align 1
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%index.next = add i64 %index, 4
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%0 = icmp eq i64 undef, %index.next
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br i1 %0, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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br i1 undef, label %for.end, label %for.body.preheader1
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for.body.preheader1: ; preds = %middle.block
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%scevgep2 = getelementptr i8, i8* %dst, i64 0
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br label %for.body
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for.body: ; preds = %for.body, %for.body.preheader1
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%lsr.iv3 = phi i8* [ %scevgep2, %for.body.preheader1 ], [ %scevgep4, %for.body ]
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store i8 undef, i8* %lsr.iv3, align 1
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%scevgep4 = getelementptr i8, i8* %lsr.iv3, i64 1
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br label %for.body
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for.end: ; preds = %middle.block, %entry
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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