forked from OSchip/llvm-project
f76f315436
Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356 |
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2003-08-03-PassCode.td | ||
2006-09-18-LargeInt.td | ||
2010-03-24-PrematureDefaults.td | ||
AnonDefinitionOnDemand.td | ||
AsmPredicateCondsEmission.td | ||
AsmVariant.td | ||
BitOffsetDecoder.td | ||
BitsInit.td | ||
BitsInitOverflow.td | ||
CStyleComment.td | ||
ClassInstanceValue.td | ||
ConcatenatedSubregs.td | ||
Dag.td | ||
DefmInherit.td | ||
DefmInsideMultiClass.td | ||
DuplicateFieldValues.td | ||
FieldAccess.td | ||
ForeachList.td | ||
ForeachLoop.td | ||
ForwardRef.td | ||
GeneralList.td | ||
GlobalISelEmitter.td | ||
HwModeSelect.td | ||
Include.inc | ||
Include.td | ||
IntBitInit.td | ||
LazyChange.td | ||
LetInsideMultiClasses.td | ||
ListArgs.td | ||
ListArgsSimple.td | ||
ListConversion.td | ||
ListManip.td | ||
ListOfList.td | ||
ListSlices.td | ||
LoLoL.td | ||
MultiClass.td | ||
MultiClassDefName.td | ||
MultiClassInherit.td | ||
MultiPat.td | ||
NestedForeach.td | ||
Paste.td | ||
RegisterBankEmitter.td | ||
RegisterEncoder.td | ||
SetTheory.td | ||
SiblingForeach.td | ||
Slice.td | ||
String.td | ||
SuperSubclassSameName.td | ||
TargetInstrInfo.td | ||
TargetInstrSpec.td | ||
TemplateArgRename.td | ||
Tree.td | ||
TreeNames.td | ||
TwoLevelName.td | ||
UnsetBitInit.td | ||
UnterminatedComment.td | ||
ValidIdentifiers.td | ||
cast-list-initializer.td | ||
cast.td | ||
defmclass.td | ||
eq.td | ||
eqbit.td | ||
foreach.td | ||
if-empty-list-arg.td | ||
if.td | ||
ifbit.td | ||
intrinsic-long-name.td | ||
intrinsic-struct.td | ||
intrinsic-varargs.td | ||
lisp.td | ||
list-element-bitref.td | ||
listconcat.td | ||
lit.local.cfg | ||
math.td | ||
nested-comment.td | ||
pr8330.td | ||
strconcat.td | ||
subst.td | ||
subst2.td | ||
trydecode-emission.td | ||
trydecode-emission2.td | ||
trydecode-emission3.td | ||
usevalname.td |