llvm-project/llvm/test/MC
Duncan P. N. Exon Smith 814b8e91c7 DI: Require subprogram definitions to be distinct
As a follow-up to r246098, require `DISubprogram` definitions
(`isDefinition: true`) to be 'distinct'.  Specifically, add an assembler
check, a verifier check, and bitcode upgrading logic to combat testcase
bitrot after the `DIBuilder` change.

While working on the testcases, I realized that
test/Linker/subprogram-linkonce-weak-odr.ll isn't relevant anymore.  Its
purpose was to check for a corner case in PR22792 where two subprogram
definitions match exactly and share the same metadata node.  The new
verifier check, requiring that subprogram definitions are 'distinct',
precludes that possibility.

I updated almost all the IR with the following script:

    git grep -l -E -e '= !DISubprogram\(.* isDefinition: true' |
    grep -v test/Bitcode |
    xargs sed -i '' -e 's/= \(!DISubprogram(.*, isDefinition: true\)/= distinct \1/'

Likely some variant of would work for out-of-tree testcases.

llvm-svn: 246327
2015-08-28 20:26:49 +00:00
..
AArch64 [AArch64] Improve short-form diags on long-form Match_InvalidOperand. 2015-08-19 17:40:19 +00:00
AMDGPU AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructions 2015-08-07 22:00:56 +00:00
ARM DI: Require subprogram definitions to be distinct 2015-08-28 20:26:49 +00:00
AsmParser Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI 2015-08-10 19:01:27 +00:00
COFF Revert "Centralize the information about which object format we are using." 2015-08-14 15:48:41 +00:00
Disassembler [llvm-mc] Ignore opcode size prefix in 64-bit CALL disassembly 2015-08-26 16:20:29 +00:00
ELF DI: Require subprogram definitions to be distinct 2015-08-28 20:26:49 +00:00
Hexagon [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing. 2015-06-05 16:00:11 +00:00
MachO [MC] Convert tests to use llvm-readobj --macho-version-min. 2015-08-28 12:40:05 +00:00
Markup
Mips [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions 2015-08-20 11:51:49 +00:00
PowerPC Scalar to vector conversions using direct moves 2015-08-13 17:40:44 +00:00
Sparc [Sparc]: correct the 'set' synthetic instruction 2015-08-20 16:16:16 +00:00
SystemZ [SystemZ] Add z13 vector facility and MC support 2015-05-05 19:23:40 +00:00
X86 [X86] Add support for mmword memory operand size for Intel-syntax x86 assembly 2015-08-24 10:26:54 +00:00