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llvm-project/llvm/test/MC/RISCV
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Luis Marques c3bf3d14ea [RISCV] Add support for RVC HINT instructions 
The hint instructions are enabled by default (if the standard C extension is 
enabled). To disable them pass -mattr=-rvc-hints.

Differential Revision: https://reviews.llvm.org/D62592

llvm-svn: 369528
 		2019-08-21 14:00:58 +00:00
..
align.s [RISCV] Avoid overflow when determining number of nops for code align 2019-07-16 04:40:25 +00:00
cfi-regs-invalid.s [RISCV] Fix RISCVAsmParser::ParseRegister and add tests 2019-03-17 12:00:58 +00:00
cfi-regs-valid.s [RISCV] Fix RISCVAsmParser::ParseRegister and add tests 2019-03-17 12:00:58 +00:00
cnop.s
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compress-cjal.s
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compress-rv32d.s
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compress-rv32f.s
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compress-rv32i.s [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
compress-rv64i.s
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compressed-relocations.s
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csr-aliases.s [RISCV] Allow access to FP CSRs without F extension 2019-03-08 23:01:08 +00:00
data-directives-invalid.s
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data-directives-valid.s
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elf-flags.s [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
elf-header.s
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empty-string.s Move some llvm-mc tests where they belong 2019-02-05 20:12:48 +00:00
fde-reloc.s [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location 2019-08-20 12:32:31 +00:00
fixups-compressed.s
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fixups-diagnostics.s
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fixups-expr.s
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fixups.s [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
function-call-invalid.s [RISCV] Add pseudo instruction for calls with explicit register 2019-06-26 10:35:58 +00:00
function-call.s [RISCV] Add pseudo instruction for calls with explicit register 2019-06-26 10:35:58 +00:00
hilo-constaddr-expr.s
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hilo-constaddr.s
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linker-relaxation.s [RISCV] Don't force absolute FK_Data_X fixups to relocs 2019-08-19 13:23:02 +00:00
lit.local.cfg [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
lla-invalid.s [RISCV] Support assembling @plt symbol operands 2019-04-02 12:47:20 +00:00
machine-csr-names-invalid.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
machine-csr-names.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
mattr-invalid-combination.s [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
option-invalid.s [RISCV] Support .option push and .option pop 2018-11-28 16:39:14 +00:00
option-mix.s [RISCV][MC] Find matching pcrel_hi fixup in more cases. 2019-03-12 18:14:16 +00:00
option-pushpop.s [RISCV] Add R_RISCV_RELAX relocation to all possible relax candidates. 2019-01-21 05:27:09 +00:00
option-relax.s [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation) 2019-04-01 02:38:27 +00:00
option-rvc.s
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pcrel-lo12-invalid.s [RISCV] Properly evaluate fixup_riscv_pcrel_lo12 2018-12-20 14:52:15 +00:00
priv-invalid.s
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priv-valid.s
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relocations.s [RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers 2019-04-23 14:46:13 +00:00
rv32-machine-csr-names.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
rv32-relaxation.s
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rv32-user-csr-names.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
rv32a-invalid.s [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
rv32a-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv32c-aliases-valid.s
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rv32c-fuzzed-invalid.s
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rv32c-invalid.s [RISCV] Add support for RVC HINT instructions 2019-08-21 14:00:58 +00:00
rv32c-only-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv32c-valid.s [RISCV] Add UNIMP instruction (32- and 16-bit forms) 2018-11-30 13:39:17 +00:00
rv32d-invalid.s [RISCV] Support assembling TLS add and associated modifiers 2019-04-04 14:13:37 +00:00
rv32d-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv32dc-invalid.s
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rv32dc-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv32e-invalid.s [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
rv32e-valid.s [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
rv32f-invalid.s [RISCV] Support assembling TLS add and associated modifiers 2019-04-04 14:13:37 +00:00
rv32f-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv32fc-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rv32fc-invalid.s
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rv32fc-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv32i-aliases-invalid.s [RISCV] Attempt to make rv{32,64}i-aliases-invalid.s less flaky 2019-07-30 13:40:51 +00:00
rv32i-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rv32i-invalid.s [RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiers 2019-04-23 14:46:13 +00:00
rv32i-valid.s [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
rv32m-invalid.s
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rv32m-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv64-machine-csr-names.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
rv64-relaxation.s
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rv64-user-csr-names.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
rv64a-aliases-valid.s [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
rv64a-invalid.s [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
rv64a-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv64c-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rv64c-hints-valid.s [RISCV] Add support for RVC HINT instructions 2019-08-21 14:00:58 +00:00
rv64c-invalid.s [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types 2018-09-13 18:37:23 +00:00
rv64c-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv64d-aliases-valid.s
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rv64d-invalid.s
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rv64d-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv64dc-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv64f-aliases-valid.s
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rv64f-invalid.s
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rv64f-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rv64i-aliases-invalid.s [RISCV] Attempt to make rv{32,64}i-aliases-invalid.s less flaky 2019-07-30 13:40:51 +00:00
rv64i-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rv64i-invalid.s [RISCV] Support assembling TLS add and associated modifiers 2019-04-04 14:13:37 +00:00
rv64i-pseudos.s [RISCV] Implement pseudo instructions for load/store from a symbol address. 2019-02-20 03:31:32 +00:00
rv64i-valid.s [RISCV][MC] Add support for evaluating constant symbols as immediates 2019-01-10 15:33:17 +00:00
rv64m-valid.s [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands 2018-09-06 13:41:04 +00:00
rva-aliases-invalid.s [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
rva-aliases-valid.s [RISCV] Add Custom Parser for Atomic Memory Operands 2019-08-01 12:42:31 +00:00
rvc-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rvc-hints-invalid.s [RISCV] Add support for RVC HINT instructions 2019-08-21 14:00:58 +00:00
rvc-hints-valid.s [RISCV] Add support for RVC HINT instructions 2019-08-21 14:00:58 +00:00
rvd-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rvd-pseudos.s [RISCV] Implement pseudo instructions for load/store from a symbol address. 2019-02-20 03:31:32 +00:00
rvdc-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rvf-aliases-valid.s [RISCV] Add implied zero offset load/store alias patterns 2019-02-21 14:09:34 +00:00
rvf-pseudos.s [RISCV] Implement pseudo instructions for load/store from a symbol address. 2019-02-20 03:31:32 +00:00
rvf-user-csr-names.s [RISCV] Allow access to FP CSRs without F extension 2019-03-08 23:01:08 +00:00
rvi-aliases-valid.s [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
rvi-alternate-abi-names.s [RISCV] Allow fp as an alias of s0 2019-03-11 21:35:26 +00:00
rvi-pseudos-invalid.s [RISCV][NFC] Correct RUN in rvi-pseudos-invalid.s 2019-07-23 17:14:42 +00:00
rvi-pseudos.s [RISCV] Allow parsing of bare symbols with offsets 2019-08-16 12:00:56 +00:00
supervisor-csr-names.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
tail-call-invalid.s
…
tail-call.s [RISCV] Support assembling @plt symbol operands 2019-04-02 12:47:20 +00:00
target-abi-invalid.s [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
target-abi-valid.s [llvm-readobj] Change -long-option to --long-option in tests. NFC 2019-05-01 05:27:20 +00:00
user-csr-names-invalid.s [RISCV] Allow access to FP CSRs without F extension 2019-03-08 23:01:08 +00:00
user-csr-names.s [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00