forked from OSchip/llvm-project
118 lines
4.0 KiB
C++
118 lines
4.0 KiB
C++
//===-- RISCVTargetStreamer.cpp - RISCV Target Streamer Methods -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides RISCV specific target streamer methods.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetStreamer.h"
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#include "RISCVSubtarget.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/RISCVAttributes.h"
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using namespace llvm;
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RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
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void RISCVTargetStreamer::finish() { finishAttributeSection(); }
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void RISCVTargetStreamer::emitDirectiveOptionPush() {}
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void RISCVTargetStreamer::emitDirectiveOptionPop() {}
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void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
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void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
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void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
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void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
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void RISCVTargetStreamer::finishAttributeSection() {}
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void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
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StringRef String) {}
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void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
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unsigned IntValue,
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StringRef StringValue) {}
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void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
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if (STI.hasFeature(RISCV::FeatureRV32E))
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emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
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else
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emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
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std::string Arch = "rv32";
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if (STI.hasFeature(RISCV::Feature64Bit))
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Arch = "rv64";
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if (STI.hasFeature(RISCV::FeatureRV32E))
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Arch += "e1p9";
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else
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Arch += "i2p0";
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if (STI.hasFeature(RISCV::FeatureStdExtM))
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Arch += "_m2p0";
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if (STI.hasFeature(RISCV::FeatureStdExtA))
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Arch += "_a2p0";
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if (STI.hasFeature(RISCV::FeatureStdExtF))
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Arch += "_f2p0";
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if (STI.hasFeature(RISCV::FeatureStdExtD))
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Arch += "_d2p0";
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if (STI.hasFeature(RISCV::FeatureStdExtC))
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Arch += "_c2p0";
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emitTextAttribute(RISCVAttrs::ARCH, Arch);
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}
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// This part is for ascii assembly output
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RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS)
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: RISCVTargetStreamer(S), OS(OS) {}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
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OS << "\t.option\tpush\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
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OS << "\t.option\tpop\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
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OS << "\t.option\tpic\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
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OS << "\t.option\tnopic\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
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OS << "\t.option\trvc\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
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OS << "\t.option\tnorvc\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
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OS << "\t.option\trelax\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
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OS << "\t.option\tnorelax\n";
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}
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void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
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OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
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}
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void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
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StringRef String) {
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OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
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}
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void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
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unsigned IntValue,
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StringRef StringValue) {}
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void RISCVTargetAsmStreamer::finishAttributeSection() {}
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