forked from OSchip/llvm-project
3149ec07c0
This ensures that we never encode an instruction which is unavailable, such as if we explicitly insert a forbidden instruction when lowering. This is particularly important on RISC-V given its high degree of modularity, and will become increasingly important as new standard extensions appear. Reviewed By: asb, lenary Differential Revision: https://reviews.llvm.org/D85015 |
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CMakeLists.txt | ||
LLVMBuild.txt | ||
RISCVAsmBackend.cpp | ||
RISCVAsmBackend.h | ||
RISCVELFObjectWriter.cpp | ||
RISCVELFStreamer.cpp | ||
RISCVELFStreamer.h | ||
RISCVFixupKinds.h | ||
RISCVInstPrinter.cpp | ||
RISCVInstPrinter.h | ||
RISCVMCAsmInfo.cpp | ||
RISCVMCAsmInfo.h | ||
RISCVMCCodeEmitter.cpp | ||
RISCVMCExpr.cpp | ||
RISCVMCExpr.h | ||
RISCVMCTargetDesc.cpp | ||
RISCVMCTargetDesc.h | ||
RISCVTargetStreamer.cpp | ||
RISCVTargetStreamer.h |