forked from OSchip/llvm-project
84 lines
3.5 KiB
TableGen
84 lines
3.5 KiB
TableGen
//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Subtarget features.
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//
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def Feature64Bit : SubtargetFeature<"64bit","Is64Bit", "true",
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"Enable 64-bit instructions">;
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Has64BitRegs", "true",
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"Enable 64-bit registers [beta]">;
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
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"Enable Altivec instructions">;
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def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
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"Enable GPUL instructions">;
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def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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"Enable the fsqrt instruction">;
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def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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"Enable the stfiwx instruction">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "PPCRegisterInfo.td"
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include "PPCSchedule.td"
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include "PPCInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// PowerPC processors supported.
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//
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def : Processor<"generic", G3Itineraries, []>;
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def : Processor<"601", G3Itineraries, []>;
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def : Processor<"602", G3Itineraries, []>;
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def : Processor<"603", G3Itineraries, []>;
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def : Processor<"603e", G3Itineraries, []>;
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def : Processor<"603ev", G3Itineraries, []>;
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def : Processor<"604", G3Itineraries, []>;
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def : Processor<"604e", G3Itineraries, []>;
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def : Processor<"620", G3Itineraries, []>;
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def : Processor<"g3", G3Itineraries, []>;
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def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
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def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
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def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
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def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
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def : Processor<"750", G3Itineraries, []>;
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def : Processor<"970", G5Itineraries,
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[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def : Processor<"g5", G5Itineraries,
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[FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
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Feature64Bit /*, Feature64BitRegs */]>;
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def PPC : Target {
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// Pointers on PPC are 32-bits in size.
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let PointerType = i32;
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// According to the Mach-O Runtime ABI, these regs are nonvolatile across
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// calls
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let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
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F30, F31, CR2, CR3, CR4, LR];
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// Pull in Instruction Info:
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let InstructionSet = PowerPCInstrInfo;
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}
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