llvm-project/llvm/test/CodeGen
Craig Topper 76f44015e7 [X86] Add a combine to recognize when we have two insert subvectors that together write the whole vector, but the starting vector isn't undef.
In this case we should replace the starting vector with undef.

llvm-svn: 312462
2017-09-04 01:13:36 +00:00
..
AArch64 [LoopVectorizer] Use two step casting for float to pointer types. 2017-09-01 15:36:00 +00:00
AMDGPU [AMDGPU] Testcase for computeKnownBits recursion. NFC. 2017-09-01 22:25:22 +00:00
ARC [ARC] Add ARC backend. 2017-08-24 15:40:33 +00:00
ARM LiveIntervalAnalysis: Fix alias regunit reserved definition 2017-09-01 18:36:26 +00:00
AVR [AVR] Use the correct register classes for 16-bit atomic operations 2017-08-24 00:14:38 +00:00
BPF Canonicalize the representation of empty an expression in DIGlobalVariableExpression 2017-08-30 18:06:51 +00:00
Generic [MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0 2017-09-01 22:17:14 +00:00
Hexagon [Hexagon] Check for potential bank conflicts in post-RA scheduling 2017-08-28 18:36:21 +00:00
Inputs
Lanai
MIR [codeview] Generalize DIExpression parsing to handle load chains 2017-08-31 15:56:49 +00:00
MSP430
Mips Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2017-09-01 14:27:20 +00:00
NVPTX Canonicalize the representation of empty an expression in DIGlobalVariableExpression 2017-08-30 18:06:51 +00:00
Nios2
PowerPC Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2017-09-01 14:27:20 +00:00
SPARC Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2017-09-01 14:27:20 +00:00
SystemZ [SystemZ, MachineScheduler] Improve post-RA scheduling. 2017-08-17 08:33:44 +00:00
Thumb Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2017-09-01 14:27:20 +00:00
Thumb2 [ARM] Call setBooleanContents(ZeroOrOneBooleanContent) 2017-08-22 11:02:37 +00:00
WebAssembly [WebAssembly] Refactor load ISel tablegen patterns into classes 2017-08-31 21:51:48 +00:00
WinEH
X86 [X86] Add a combine to recognize when we have two insert subvectors that together write the whole vector, but the starting vector isn't undef. 2017-09-04 01:13:36 +00:00
XCore