forked from OSchip/llvm-project
985dc0dd64
This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921 |
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| Analysis | ||
| Archive | ||
| AsmParser | ||
| Bitcode | ||
| CodeGen | ||
| DebugInfo | ||
| ExecutionEngine | ||
| Linker | ||
| MC | ||
| Object | ||
| Support | ||
| TableGen | ||
| Target | ||
| Transforms | ||
| VMCore | ||
| CMakeLists.txt | ||
| LLVMBuild.txt | ||
| Makefile | ||