..
add.v2i16.ll
AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting
2020-07-26 09:55:34 -04:00
amdgpu-irtranslator.ll
AMDGPU/GlobalISel: Remove unnecesssary REQUIREs
2019-05-29 13:14:35 +00:00
andn2.ll
AMDGPU: Add flag to disable promotion of uniform i16 ops
2020-08-24 14:39:27 -04:00
artifact-combiner-anyext.mir
AMDGPU/GlobalISel: Remove -global-isel-abort=0 from some tests
2020-03-15 17:22:34 -04:00
artifact-combiner-build-vector.mir
GlobalISel: Revisit users of other merge opcodes in artifact combiner
2020-08-17 13:56:53 -04:00
artifact-combiner-concat-vectors.mir
GlobalISel: Revisit users of other merge opcodes in artifact combiner
2020-08-17 13:56:53 -04:00
artifact-combiner-extract.mir
GlobalISel: Partially implement lower for G_EXTRACT
2019-10-06 01:37:35 +00:00
artifact-combiner-sext.mir
GlobalISel: Combine G_UNMERGE_VALUES with G_TRUNC
2020-05-09 16:14:32 -04:00
artifact-combiner-trunc.mir
[GlobalISel] combine trunc(trunc) pattern
2020-04-08 11:58:28 +02:00
artifact-combiner-unmerge-values.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
artifact-combiner-zext.mir
GlobalISel: Handle zext(sext x) in artifact combiner
2020-08-07 16:37:46 -04:00
ashr.ll
AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting
2020-07-26 09:55:34 -04:00
bool-legalization.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
bswap.ll
AMDGPU/GlobalISel: Insert readfirstlane on SGPR returns
2020-03-10 11:18:48 -04:00
combine-amdgpu-cvt-f32-ubyte.mir
AMDGPU/GlobalISel: Combines for V_CVT_F32_UBYTE[0-3]
2020-04-13 19:18:19 -04:00
combine-ashr-narrow.mir
AMDGPU/GlobalISel: Introduce post-legalize combiner
2020-02-24 22:12:12 -05:00
combine-ext-legalizer.mir
[GlobalISel] Combine sext([sz]ext) -> [sz]ext, zext(zext) -> zext
2020-04-08 11:24:29 +02:00
combine-itofp.mir
AMDGPU/GlobalISel: Fix asserts on non-s32 sitofp/uitofp sources
2020-06-23 10:00:35 -04:00
combine-lshr-narrow.mir
AMDGPU/GlobalISel: Introduce post-legalize combiner
2020-02-24 22:12:12 -05:00
combine-shl-from-extend-narrow.postlegal.mir
GlobalISel: Reduce G_SHL width if source is extension
2020-08-24 09:42:40 -04:00
combine-shl-from-extend-narrow.prelegal.mir
GlobalISel: Reduce G_SHL width if source is extension
2020-08-24 09:42:40 -04:00
combine-shl-narrow.mir
AMDGPU/GlobalISel: Introduce post-legalize combiner
2020-02-24 22:12:12 -05:00
constant-bus-restriction.ll
AMDGPU/GlobalISel: Address some test fixmes that don't fail now
2020-07-18 10:54:39 -04:00
cvt_f32_ubyte.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
divergent-control-flow.ll
AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT
2020-08-18 09:28:01 -04:00
dummy-target.ll
AMDGPU/GlobalISel: Don't assert in LegalizerInfo constructor
2020-07-26 23:01:28 -04:00
dynamic-alloca-divergent.ll
AMDGPU/GlobalISel: Work around verifier error in test
2020-07-09 10:24:16 -04:00
dynamic-alloca-uniform.ll
AMDGPU: Correct prolog SP initialization logic
2020-08-05 15:47:53 -04:00
extractelement-stack-lower.ll
[Scheduling] Create the missing dependency edges for store cluster
2020-08-07 04:58:03 +00:00
extractelement.i8.ll
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT
2020-08-02 10:42:07 -04:00
extractelement.i16.ll
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT
2020-08-02 10:42:07 -04:00
extractelement.i128.ll
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT
2020-08-02 10:42:07 -04:00
extractelement.ll
GlobalISel: Implement fewerElementsVector for G_EXTRACT_VECTOR_ELT
2020-08-06 14:33:16 -04:00
flat-scratch-init.ll
AMDGPU: Annotate functions that have stack objects
2020-05-19 18:51:00 -04:00
floor.f64.ll
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI
2020-02-05 14:32:01 -05:00
fma.ll
AMDGPU/GlobalISel: Add some end to end tests for fma selection
2020-03-24 21:23:37 -04:00
fmax_legacy.ll
AMDGPU/GlobalISel: Introduce post-legalize combiner
2020-02-24 22:12:12 -05:00
fmin_legacy.ll
AMDGPU/GlobalISel: Introduce post-legalize combiner
2020-02-24 22:12:12 -05:00
fmul.v2f16.ll
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
fpow.ll
[AMDGPU] Remove dubious logic in bidirectional list scheduler
2020-02-28 21:35:34 +00:00
frem.ll
AMDGPU/GlobalISel: Lower G_FREM
2020-08-10 10:10:46 +02:00
function-returns.ll
AMDGPU/GlobalISel: Add some missing return tests
2020-07-06 09:01:18 -04:00
global-value.illegal.ll
AMDGPU/GlobalISel: Allow arbitrary global values
2020-02-17 11:32:28 -08:00
global-value.ll
[AMDGPU] Enable .rodata for amdpal os
2020-08-14 09:05:48 +02:00
hip.extern.shared.array.ll
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
image_ls_mipmap_zero.a16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
image_ls_mipmap_zero.ll
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
inline-asm.ll
[GlobalISel][InlineAsm] Add support for matching input constraints
2020-06-30 10:49:05 +02:00
insertelement-stack-lower.ll
[Scheduling] Create the missing dependency edges for store cluster
2020-08-07 04:58:03 +00:00
insertelement.i8.ll
GlobalISel: Implement bitcast action for G_INSERT_VECTOR_ELT
2020-08-11 10:39:14 -04:00
insertelement.i16.ll
GlobalISel: Implement bitcast action for G_INSERT_VECTOR_ELT
2020-08-11 10:39:14 -04:00
insertelement.large.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
insertelement.ll
[AMDGPU] Make GCNRegBankReassign assign based on subreg banks
2020-08-04 12:54:44 +09:00
inst-select-abs.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-add.mir
TableGen/GlobalISel: Allow output instructions with multiple defs
2020-07-27 18:31:13 -04:00
inst-select-add.s16.mir
[AMDGPU][MC][GFX8+] Enabled clamp for v_add_u16, v_sub_u16 and v_subrev_u16
2020-05-25 19:55:38 +03:00
inst-select-amdgcn.class.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-amdgcn.class.s16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cos.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.cos.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.cvt.pk.i16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pk.u16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pknorm.i16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pknorm.u16.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.cvt.pkrtz.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.ds.swizzle.mir
TableGen/GlobalISel: Add way for SDNodeXForm to work on timm
2020-01-09 17:37:52 -05:00
inst-select-amdgcn.exp.mir
AMDGPU/GlobalISel: Fix some broken YAML in MIR test
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.fmad.ftz.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
inst-select-amdgcn.fmed3.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
inst-select-amdgcn.fmed3.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.fract.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.fract.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.groupstaticsize.mir
AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize
2020-08-18 09:28:01 -04:00
inst-select-amdgcn.ldexp.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.ldexp.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.mbcnt.lo.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.mul.u24.mir
[AMDGPU][MC][GFX8+] Enabled clamp for v_mul_i32_i24_e64 and v_mul_u32_u24_e64
2020-05-22 14:11:31 +03:00
inst-select-amdgcn.rcp.legacy.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.rcp.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.rcp.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.readfirstlane.mir
AMDGPU/GlobalISel: Fix readfirstlane pattern import
2020-01-07 11:07:08 -05:00
inst-select-amdgcn.reloc.constant.mir
AMDGPU/GlobalISel: Handle llvm.amdgcn.reloc.constant
2020-07-29 14:24:21 -04:00
inst-select-amdgcn.rsq.clamp.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.rsq.legacy.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.rsq.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.rsq.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.s.barrier.mir
AMDGPU/GlobalISel: Try generated matcher with intrinsics
2019-07-02 14:52:16 +00:00
inst-select-amdgcn.s.sendmsg.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.sffbh.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-amdgcn.sin.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgcn.sin.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-amdgpu-atomic-cmpxchg-flat.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-amdgpu-ffbh-u32.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-and.mir
AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT
2020-08-18 09:28:01 -04:00
inst-select-anyext.mir
AMDGPU/GlobalISel: Fix selecting broken copies for s32->s64 anyext
2020-08-03 08:36:41 -04:00
inst-select-ashr.mir
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
inst-select-ashr.s16.mir
AMDGPU/GlobalISel: Legalize 16-bit shift amounts to s16
2020-04-11 18:12:26 -04:00
inst-select-ashr.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-atomic-cmpxchg-local.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-atomic-cmpxchg-region.mir
AMDGPU/GlobalISel: Legalize GDS atomics
2020-07-26 10:03:34 -04:00
inst-select-atomicrmw-add-flat.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-atomicrmw-add-global.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-atomicrmw-fadd-local.mir
AMDGPU/GlobalISel: Fix test failure in release build
2020-06-06 11:01:18 -04:00
inst-select-atomicrmw-fadd-region.mir
AMDGPU/GlobalISel: Legalize GDS atomics
2020-07-26 10:03:34 -04:00
inst-select-atomicrmw-xchg-local.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-atomicrmw-xchg-region.mir
AMDGPU/GlobalISel: Legalize GDS atomics
2020-07-26 10:03:34 -04:00
inst-select-bitcast.mir
AMDGPU/GlobalISel: Prepare some tests for store selection
2019-07-09 14:30:57 +00:00
inst-select-bitreverse.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-br.mir
AMDGPU/GlobalISel: Select G_BRCOND for scc conditions
2019-07-01 15:39:27 +00:00
inst-select-brcond.mir
AMDGPU/GlobalISel: Remove old hacks for boolean selection
2020-08-03 09:04:14 -04:00
inst-select-bswap.mir
AMDGPU/GlobalISel: Handle G_BSWAP
2020-02-14 09:09:44 -08:00
inst-select-build-vector-trunc.v2s16.mir
AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting
2020-07-26 09:55:34 -04:00
inst-select-build-vector.mir
AMDGPU/GlobalISel: Remove some selection tests which should be invalid
2020-06-30 19:18:01 -04:00
inst-select-concat-vectors.mir
AMDGPU/GlobalISel: Fixed handling of non-standard vectors
2020-05-27 15:44:09 -07:00
inst-select-constant.mir
AMDGPU/GlobalISel: Add selection tests for pointer constants
2020-08-19 10:23:56 -04:00
inst-select-copy.mir
AMDGPU/GlobalISel: Fix assert on copy to vcc
2020-08-06 09:41:14 -04:00
inst-select-ctlz-zero-undef.mir
AMDGPU/GlobalISel: Select G_CTLZ_ZERO_UNDEF
2020-02-12 16:19:45 -08:00
inst-select-ctpop.mir
AMDGPU/GlobalISel: Fix missing test for select of s64 scalar G_CTPOP
2020-02-07 13:15:48 -05:00
inst-select-cttz-zero-undef.mir
AMDGPU/GlobalISel: Select G_CTTZ_ZERO_UNDEF
2020-02-12 16:19:46 -08:00
inst-select-extract-vector-elt.mir
[AMDGPU] Do not use undef on indirect source
2020-07-30 10:41:59 -07:00
inst-select-extract.mir
AMDGPU/GlobalISel: Add some missing tests for extract selection
2020-07-28 16:49:55 -04:00
inst-select-fabs.mir
AMDGPU/GlobalISel: Fix selection of scalar f64 G_FABS
2020-04-14 22:05:22 -04:00
inst-select-fadd.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fadd.s32.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fadd.s64.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fcanonicalize.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fceil.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fceil.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fcmp.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fcmp.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fconstant.mir
AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT
2020-08-18 09:28:01 -04:00
inst-select-fexp2.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-ffloor.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-ffloor.s32.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-ffloor.s64.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fma.s32.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmad.s32.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
inst-select-fmaxnum-ieee.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmaxnum-ieee.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmaxnum-ieee.v2s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmaxnum.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmaxnum.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmaxnum.v2s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fminnum-ieee.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fminnum-ieee.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fminnum-ieee.v2s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fminnum.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fminnum.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fminnum.v2s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmul.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fmul.v2s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fneg.mir
TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands
2020-04-14 22:05:22 -04:00
inst-select-fptosi.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fptoui.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-frame-index.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-freeze.mir
AMDGPU/GlobalISel: Select G_FREEZE
2020-07-16 11:10:48 +02:00
inst-select-frint.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-frint.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-fshr.mir
AMDGPU/GlobalISel: Basic legalize rules for G_FSHR
2020-03-30 11:53:01 -07:00
inst-select-icmp.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-icmp.s16.mir
AMDGPU/GlobalISel: Fix missing test for s16 icmp
2020-01-07 16:36:31 -05:00
inst-select-icmp.s64.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
inst-select-implicit-def.mir
[AMDGPU] Use SGPR instead of SReg classes
2020-04-23 11:45:22 +01:00
inst-select-insert-vector-elt.mir
AMDGPU: Don't run indexing mode switches with exec = 0
2020-06-02 13:47:48 -04:00
inst-select-insert.mir
[AMDGPU] Use SGPR instead of SReg classes
2020-04-23 11:45:22 +01:00
inst-select-insert.xfail.mir
AMDGPU/GlobalISel: Don't assert on G_INSERT > 128-bits
2020-07-25 10:05:44 -04:00
inst-select-intrinsic-trunc.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-intrinsic-trunc.s16.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-inttoptr.mir
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
inst-select-load-atomic-flat.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-load-atomic-global.mir
AMDGPU: Fix matching wrong offsets for global atomic loads
2020-08-15 12:12:17 -04:00
inst-select-load-atomic-local.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-load-constant.mir
AMDGPU/GlobalISel: Workaround some load/store type selection patterns
2020-06-15 07:42:20 -04:00
inst-select-load-flat.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-load-global-saddr.mir
AMDGPU/GlobalISel: Match global saddr addressing mode
2020-08-17 15:48:06 -04:00
inst-select-load-global.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-load-global.s96.mir
AMDGPU/GlobalISel: Workaround some load/store type selection patterns
2020-06-15 07:42:20 -04:00
inst-select-load-local-128.mir
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
inst-select-load-local.mir
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
inst-select-load-private.mir
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
inst-select-load-smrd.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-lshr.mir
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
inst-select-lshr.s16.mir
AMDGPU/GlobalISel: Legalize 16-bit shift amounts to s16
2020-04-11 18:12:26 -04:00
inst-select-lshr.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-merge-values.mir
AMDGPU/GlobalISel: Remove some selection tests which should be invalid
2020-06-30 19:18:01 -04:00
inst-select-mul.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-or.mir
AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT
2020-08-18 09:28:01 -04:00
inst-select-pattern-add3.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-pattern-and-or.mir
AMDGPU/GlobalISel: Add select patterns for v_and_or_b32
2020-03-24 20:47:54 -04:00
inst-select-pattern-or3.mir
AMDGPU/GlobalISel: Fix xnor matching
2020-02-21 11:42:49 -05:00
inst-select-pattern-smed3.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-smed3.s16.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-umed3.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-umed3.s16.mir
AMDGPU/GlobalISel: Fix import of integer med3
2020-01-09 10:29:32 -05:00
inst-select-pattern-xor3.mir
AMDGPU/GlobalISel: Fix bug in test register bank
2020-05-19 22:52:59 -04:00
inst-select-phi.mir
AMDGPU/GlobalISel: Remove old hacks for boolean selection
2020-08-03 09:04:14 -04:00
inst-select-ptr-add.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-ptrmask.mir
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
inst-select-ptrtoint.mir
AMDGPU/GlobalISel: Don't use XEXEC class for SGPRs
2020-01-12 22:44:51 -05:00
inst-select-returnaddress.mir
AMDGPU/GlobalISel: Select llvm.returnaddress
2020-08-04 17:14:38 -04:00
inst-select-scalar-packed.xfail.mir
AMDGPU/GlobalISel: Fix mishandling SGPR v2s16 add/sub/mul
2020-03-09 22:51:54 -04:00
inst-select-select.mir
AMDGPU/GlobalISel: Eliminate SelectVOP3Mods_f32
2020-01-27 17:53:54 -05:00
inst-select-sext-inreg.mir
AMDGPU/GlobalISel: Select G_SEXT_INREG
2020-02-04 13:23:53 -08:00
inst-select-sext.mir
AMDGPU/GlobalISel: Remove extension legality hacks
2020-02-04 12:50:47 -08:00
inst-select-shl.mir
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
inst-select-shl.s16.mir
AMDGPU/GlobalISel: Legalize 16-bit shift amounts to s16
2020-04-11 18:12:26 -04:00
inst-select-shl.v2s16.mir
AMDGPU/GlobalISel: Select VOP3P instructions
2020-02-21 13:35:40 -05:00
inst-select-shuffle-vector.v2s16.mir
AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16
2020-02-21 21:16:39 +00:00
inst-select-sitofp.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-smax.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-smin.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-smulh.mir
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
inst-select-store-atomic-flat.mir
TableGen/GlobalISel: Hack the operand order for atomic_store
2020-08-11 10:22:44 -04:00
inst-select-store-atomic-local.mir
TableGen/GlobalISel: Hack the operand order for atomic_store
2020-08-11 10:22:44 -04:00
inst-select-store-flat.mir
TableGen/GlobalISel: Hack the operand order for atomic_store
2020-08-11 10:22:44 -04:00
inst-select-store-global.mir
TableGen/GlobalISel: Hack the operand order for atomic_store
2020-08-11 10:22:44 -04:00
inst-select-store-global.s96.mir
AMDGPU/GlobalISel: Split 96-bit load/store select tests out
2020-02-12 09:58:37 -05:00
inst-select-store-local.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-store-private.mir
GlobalISel: Make known bits/alignment API more consistent
2020-06-05 14:57:22 -04:00
inst-select-sub.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-trunc.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
inst-select-trunc.v2s16.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
inst-select-uadde.gfx10.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-uadde.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-uaddo.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-uitofp.mir
GlobalISel: Infer nofpexcept flag during selection for non-strict ops
2020-06-05 13:59:46 -04:00
inst-select-umax.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-umin.mir
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
inst-select-umulh.mir
AMDGPU/GlobalISel: Fix tablegen selection for scalar bin ops
2020-01-29 08:55:54 -08:00
inst-select-unmerge-values.mir
AMDGPU/GlobalISel: Ensure subreg is valid when selecting G_UNMERGE_VALUES
2020-08-04 12:27:34 -04:00
inst-select-usube.gfx10.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-usube.mir
AMDGPU/GlobalISel: Select G_UADDE/G_USUBE
2020-01-06 18:27:52 -05:00
inst-select-usubo.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
inst-select-xor.mir
AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT
2020-08-18 09:28:01 -04:00
inst-select-zext.mir
AMDGPU/GlobalISel: Remove extension legality hacks
2020-02-04 12:50:47 -08:00
irtranslator-amdgcn-sendmsg.ll
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
irtranslator-amdgpu_kernel-system-sgprs.ll
AMDGPU/GlobalISel: Legalize workgroup ID intrinsics
2019-07-01 18:47:22 +00:00
irtranslator-amdgpu_kernel.ll
AMDGPU: Start interpreting byref on kernel arguments
2020-07-21 18:11:22 -04:00
irtranslator-amdgpu_ps.ll
AMDGPU/GlobalISel: Insert readfirstlane on SGPR returns
2020-03-10 11:18:48 -04:00
irtranslator-amdgpu_vs.ll
AMDGPU/GlobalISel: Insert readfirstlane on SGPR returns
2020-03-10 11:18:48 -04:00
irtranslator-atomicrmw.ll
GlobalISel: Add G_ATOMICRMW_{FADD|FSUB}
2019-07-30 23:56:30 +00:00
irtranslator-call-implicit-args.ll
GlobalISel: Add utilty for getting function argument live ins
2020-08-04 16:55:55 -04:00
irtranslator-call-return-values.ll
AMDGPU/GlobalISel: Handle call return values
2020-07-23 14:29:35 -04:00
irtranslator-call-sret.ll
[GlobalISel][CallLowering] Look through call parameters for flags
2020-08-18 08:48:56 -07:00
irtranslator-call.ll
AMDGPU/GlobalISel: Stop using G_EXTRACT in argument lowering
2020-08-06 09:55:35 -04:00
irtranslator-constantexpr.ll
GlobalISel: Fix IRTranslator for constantexpr selects
2020-05-19 09:52:48 -04:00
irtranslator-constrained-fp.ll
GlobalISel: Start defining strict FP instructions
2020-06-03 20:46:37 -04:00
irtranslator-fast-math-flags.ll
AMDGPU/GlobalISel: Legalize workitem ID intrinsics
2019-07-01 18:45:36 +00:00
irtranslator-fence.ll
GlobalISel: Add G_FENCE
2019-07-02 14:16:39 +00:00
irtranslator-fixed-function-abi-vgpr-args.ll
AMDGPU/GlobalISel: Fix fixed ABI special VGPR function arguments
2020-06-23 21:21:35 -04:00
irtranslator-function-args.ll
AMDGPU/GlobalISel: Add some tests for stack passed pointers
2020-07-23 14:38:31 -04:00
irtranslator-getelementptr.ll
[GlobalISel][IRTranslator] Follow convention and put constant offset of getelementptr arithmetic on RHS.
2020-01-29 11:37:19 -08:00
irtranslator-indirect-call.ll
AMDGPU/GlobalISel: Fix translation of indirect calls
2020-07-22 13:13:21 -04:00
irtranslator-inline-asm.ll
GlobalISel: Handle 'n' inline asm constraint
2020-07-26 09:30:41 -04:00
irtranslator-metadata.ll
GlobalISel: Don't fail translate on intrinsics with metadata
2020-07-27 19:00:25 -04:00
irtranslator-ptrmask.ll
GlobalISel: Handle EVT argument lowering correctly
2020-07-07 16:36:14 -04:00
irtranslator-readnone-intrinsic-callsite.ll
GlobalISel: Ignore callsite attributes when picking intrinsic type
2019-06-17 17:01:35 +00:00
irtranslator-sat.ll
[Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.
2020-08-07 15:09:24 +02:00
irtranslator-struct-return-intrinsics.ll
GlobalISel: Allow CSE of G_IMPLICIT_DEF
2020-02-05 17:47:21 -05:00
lds-global-non-entry-func.ll
AMDGPU: Don't hard error on LDS globals in functions
2020-03-11 15:34:11 -04:00
lds-global-value.ll
AMDGPU/GlobalISel: Look through copies in getPtrBaseWithConstantOffset
2020-08-17 12:31:38 -04:00
lds-relocs.ll
[GlobalISel] Add new combine to convert scalar G_MUL to G_SHL.
2020-01-29 13:39:00 -08:00
lds-size.ll
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
2019-09-09 17:13:44 +00:00
lds-zero-initializer.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
legalize-add.mir
AMDGPU/GlobalISel: Add tests for 96-bit add/sub/mul
2020-07-13 14:07:34 -04:00
legalize-addrspacecast.mir
GlobalISel: Add utilty for getting function argument live ins
2020-08-04 16:55:55 -04:00
legalize-amdgcn.if-invalid.mir
AMDGPU/GlobalISel: Custom lower control flow intrinsics
2019-07-01 18:40:23 +00:00
legalize-amdgcn.if.xfail.mir
AMDGPU/GlobalISel: Fix masked control flow with fallthrough blocks
2020-05-22 10:31:44 -04:00
legalize-amdgcn.rsq.clamp.mir
AMDGPU/GlobalISel: Implement expansion for rsq.clamp
2020-08-06 10:23:25 -04:00
legalize-amdgcn.wavefrontsize.mir
AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
2019-09-09 15:20:49 +00:00
legalize-and.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-anyext.mir
GlobalISel: Handle more cases in lowerUnmergeValues
2020-05-09 19:33:32 -04:00
legalize-ashr.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-atomic-cmpxchg-with-success.mir
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
2019-10-25 13:11:09 -07:00
legalize-atomic-cmpxchg.mir
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
2019-10-25 13:11:09 -07:00
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd.mir
AMDGPU/GlobalISel: Fix making LDS FP atomics legal on SI/CI
2020-06-04 16:50:19 -04:00
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-bitreverse.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-block-addr.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
legalize-brcond.mir
AMDGPU/GlobalISel: Set insert point when emitting control flow pseudos
2020-06-11 18:53:26 -04:00
legalize-bswap.mir
GlobalISel: Reimplement fewerElementsVectorBasic
2020-02-24 21:19:47 -05:00
legalize-build-vector-trunc.mir
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
2019-09-09 17:04:18 +00:00
legalize-build-vector.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-build-vector.s16.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-concat-vectors.mir
GlobalISel: Implement fewerElementsVector for G_CONCAT_VECTORS sources
2020-08-19 18:53:24 -04:00
legalize-constant.mir
AMDGPU/GlobalISel: Make 16-bit constants legal
2019-09-04 16:19:45 +00:00
legalize-ctlz-zero-undef.mir
[GlobalISel] combine G_TRUNC with G_MERGE_VALUES
2020-03-16 14:42:01 +01:00
legalize-ctlz.mir
[GlobalISel] combine G_TRUNC with G_MERGE_VALUES
2020-03-16 14:42:01 +01:00
legalize-ctpop.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-cttz-zero-undef.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-cttz.mir
GlobalISel: Fix lowering of G_CTLZ/G_CTTZ
2020-02-07 06:54:12 -08:00
legalize-extract-vector-elt.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-extract.mir
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-fabs.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fadd.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-fcanonicalize.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fceil.mir
AMDGPU/GlobalISel: Fix custom lowering of llvm.trunc.f64 for SI
2020-07-20 10:06:18 -04:00
legalize-fcmp.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fconstant.mir
AMDGPU/GlobalISel: Make 16-bit constants legal
2019-09-04 16:19:45 +00:00
legalize-fcopysign.mir
GlobalISel: Revisit users of other merge opcodes in artifact combiner
2020-08-17 13:56:53 -04:00
legalize-fcos.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fdiv.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fexp.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-fexp2.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-ffloor.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-flog.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-flog2.mir
GlobalISel: fewerElementsVector for a few more trivial ops
2019-01-25 04:03:38 +00:00
legalize-flog10.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
legalize-fma.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-fmad.s16.mir
AMDGPU/GlobalISel: Fix insert point when lowering G_FMAD
2020-03-31 19:57:06 -04:00
legalize-fmad.s32.mir
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
legalize-fmad.s64.mir
AMDGPU: Split denormal mode tracking bits
2020-02-04 10:44:21 -08:00
legalize-fmaxnum.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-fminnum.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-fmul.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-fneg.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fpext.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-fpow.mir
AMDGPU/GlobalISel: Legalize G_FPOW
2020-02-21 10:31:13 -05:00
legalize-fpowi.mir
GlobalISel: Legalize G_FPOWI
2020-07-21 18:13:04 -04:00
legalize-fptosi.mir
AMDGPU/GlobalISel: Fix custom lowering of llvm.trunc.f64 for SI
2020-07-20 10:06:18 -04:00
legalize-fptoui.mir
AMDGPU/GlobalISel: Fix custom lowering of llvm.trunc.f64 for SI
2020-07-20 10:06:18 -04:00
legalize-fptrunc.mir
AMDGPU/GlobalISel: Fix lower for f64->f16 G_FPTRUNC
2020-06-11 18:19:27 +02:00
legalize-freeze.mir
AMDGPU/GlobalISel: Fix trying to widen <3 x s1> boolean ops
2020-08-06 10:07:22 -04:00
legalize-frint.mir
AMDGPU/GlobalISel: Fix not erasing inst when lowering G_FRINT
2020-07-21 18:29:41 -04:00
legalize-fshr.mir
AMDGPU/GlobalISel: Basic legalize rules for G_FSHR
2020-03-30 11:53:01 -07:00
legalize-fsin.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fsqrt.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-fsub.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-icmp.mir
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 22:48:42 -05:00
legalize-implicit-def-s1025.mir
GlobalISel: Move code into lowering for G_MERGE_VALUES
2020-05-09 16:39:37 -04:00
legalize-implicit-def.mir
AMDGPU/GlobalISel: Fix trying to widen <3 x s1> boolean ops
2020-08-06 10:07:22 -04:00
legalize-insert-vector-elt.mir
GlobalISel: Implement fewerElementsVector for G_INSERT_VECTOR_ELT
2020-08-18 13:51:19 -04:00
legalize-insert.mir
GlobalISel: Reimplement moreElementsVectorDst
2020-08-03 09:03:48 -04:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
[update_mir_test_checks] Handle MI flags properly
2019-10-14 22:01:58 +00:00
legalize-intrinsic-round.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-intrinsic-trunc.mir
AMDGPU/GlobalISel: Fix custom lowering of llvm.trunc.f64 for SI
2020-07-20 10:06:18 -04:00
legalize-inttoptr.mir
[GlobalISel] combine trunc(trunc) pattern
2020-04-08 11:58:28 +02:00
legalize-jump-table.mir
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
legalize-llvm.amdgcn.image.dim.a16.ll
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT
2020-08-02 10:42:07 -04:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-llvm.amdgcn.image.load.2d.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
legalize-llvm.amdgcn.image.load.3d.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
legalize-llvm.amdgcn.image.sample.a16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
legalize-llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
legalize-llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
legalize-llvm.amdgcn.s.buffer.load.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-load-constant-32bit.mir
GlobalISel: Move code into lowering for G_MERGE_VALUES
2020-05-09 16:39:37 -04:00
legalize-load-constant.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-load-flat.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-load-global.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-load-local.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-load-memory-metadata.mir
CodeGen: Don't drop AA metadata when splitting MachineMemOperands
2020-08-20 16:17:30 -04:00
legalize-load-private.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-lshr.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
[GlobalISel] Combine scalar unmerge(trunc)
2020-06-02 08:56:18 +02:00
legalize-mul.mir
AMDGPU/GlobalISel: Add tests for 96-bit add/sub/mul
2020-07-13 14:07:34 -04:00
legalize-or.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-phi.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-ptr-add.mir
GlobalISel: Handle G_PTR_ADD in narrowScalar
2020-07-26 10:08:17 -04:00
legalize-ptrmask.mir
GlobalISel: Add scalarSameSizeAs LegalizeRule
2020-07-23 21:17:31 -04:00
legalize-ptrtoint.mir
AMDGPU/GlobalISel: Add some missing tests for non-power-of-2 cases
2020-02-16 22:48:42 -05:00
legalize-sadde.mir
AMDGPU/GlobalISel: Add more tests for G_SADDE/G_SSUBE
2020-03-15 16:54:40 -04:00
legalize-saddo.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-saddsat.mir
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-sdiv.mir
[AMDGPU] Fix and simplify AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl
2020-07-08 19:14:49 +01:00
legalize-select.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-sext-inreg.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-sext.mir
GlobalISel: Handle more cases in lowerUnmergeValues
2020-05-09 19:33:32 -04:00
legalize-sextload-constant-32bit.mir
GlobalISel: Move code into lowering for G_MERGE_VALUES
2020-05-09 16:39:37 -04:00
legalize-sextload-flat.mir
AMDGPU/GlobalISel: Legalize G_SEXT_INREG
2020-02-04 13:23:53 -08:00
legalize-sextload-global.mir
AMDGPU/GlobalISel: Start rewriting load/store legality rules
2020-06-06 09:59:46 -04:00
legalize-sextload-local.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-sextload-private.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-shl.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-shuffle-vector.mir
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT
2020-08-02 10:42:07 -04:00
legalize-shuffle-vector.s16.mir
GlobalISel: Implement bitcast action for G_EXTRACT_VECTOR_ELEMENT
2020-08-02 10:42:07 -04:00
legalize-sitofp.mir
AMDGPU/GlobalISel: Legalize s64->s16 G_SITOFP/G_UITOFP
2020-07-16 16:31:57 +02:00
legalize-smax.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-smin.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-smulh.mir
AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mul
2019-01-25 03:23:04 +00:00
legalize-srem.mir
[AMDGPU] Fix and simplify AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl
2020-07-08 19:14:49 +01:00
legalize-sshlsat.mir
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-ssube.mir
AMDGPU/GlobalISel: Add more tests for G_SADDE/G_SSUBE
2020-03-15 16:54:40 -04:00
legalize-ssubo.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-ssubsat.mir
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-store-global.mir
AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors
2020-08-25 09:37:41 -04:00
legalize-store.mir
AMDGPU/GlobalISel: Legalize odd sized loads with widening
2020-08-20 16:15:53 -04:00
legalize-sub.mir
AMDGPU/GlobalISel: Add tests for 96-bit add/sub/mul
2020-07-13 14:07:34 -04:00
legalize-trunc.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-uadde.mir
GlobalISel: Fix lowering for G_UADDE/G_USUBE
2020-02-26 19:10:52 -08:00
legalize-uaddo.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-uaddsat.mir
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-udiv.mir
[AMDGPU] Fix and simplify AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl
2020-07-08 19:14:49 +01:00
legalize-uitofp.mir
AMDGPU/GlobalISel: Legalize s64->s16 G_SITOFP/G_UITOFP
2020-07-16 16:31:57 +02:00
legalize-umax.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-umin.mir
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
2020-08-25 09:39:32 -04:00
legalize-umulh.mir
AMDGPU/GlobalISel: Add missing test for G_UMULH
2020-02-26 22:30:13 -05:00
legalize-unmerge-values.mir
AMDGPU/GlobalISel: Add baseline, failing unmerge tests
2020-08-24 10:07:30 -04:00
legalize-urem.mir
[AMDGPU] Fix and simplify AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl
2020-07-08 19:14:49 +01:00
legalize-ushlsat.mir
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-usube.mir
GlobalISel: Fix lowering for G_UADDE/G_USUBE
2020-02-26 19:10:52 -08:00
legalize-usubo.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-usubsat.mir
GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
2020-08-22 10:25:53 -04:00
legalize-xor.mir
AMDGPU/GlobalISel: Use different technique for sample v3s16 values
2020-08-24 10:07:30 -04:00
legalize-zext.mir
GlobalISel: Handle more cases in lowerUnmergeValues
2020-05-09 19:33:32 -04:00
legalize-zextload-constant-32bit.mir
GlobalISel: Move code into lowering for G_MERGE_VALUES
2020-05-09 16:39:37 -04:00
legalize-zextload-flat.mir
[MIPS GlobalISel] Select any extending load and truncating store
2019-02-08 14:27:23 +00:00
legalize-zextload-global.mir
AMDGPU/GlobalISel: Start rewriting load/store legality rules
2020-06-06 09:59:46 -04:00
legalize-zextload-local.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
legalize-zextload-private.mir
GlobalISel: Support narrowing zextload/sextload
2019-01-22 19:02:10 +00:00
lit.local.cfg
…
llvm.amdgcn.atomic.dec.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
llvm.amdgcn.atomic.inc.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot.
2020-07-13 13:35:34 +02:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot.
2020-07-13 13:35:34 +02:00
llvm.amdgcn.dispatch.id.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.dispatch.ptr.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.div.fmas.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
llvm.amdgcn.div.scale.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
llvm.amdgcn.ds.append.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
llvm.amdgcn.ds.consume.ll
AMDGPU/GlobalISel: Initial selection of MUBUF addr64 load/store
2020-01-27 07:13:56 -08:00
llvm.amdgcn.ds.fadd.ll
AMDGPU/GlobalISel: Look through copies in getPtrBaseWithConstantOffset
2020-08-17 12:31:38 -04:00
llvm.amdgcn.ds.fmax.ll
AMDGPU/GlobalISel: Look through copies in getPtrBaseWithConstantOffset
2020-08-17 12:31:38 -04:00
llvm.amdgcn.ds.fmin.ll
AMDGPU/GlobalISel: Look through copies in getPtrBaseWithConstantOffset
2020-08-17 12:31:38 -04:00
llvm.amdgcn.ds.gws.barrier.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.init.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.br.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.release.all.ll
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
llvm.amdgcn.ds.gws.sema.v.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.ordered.add.gfx10.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}
2020-01-13 13:09:38 -05:00
llvm.amdgcn.ds.ordered.add.ll
AMDGPU/GlobalISel: Address some test fixmes that don't fail now
2020-07-18 10:54:39 -04:00
llvm.amdgcn.ds.ordered.swap.ll
AMDGPU/GlobalISel: Address some test fixmes that don't fail now
2020-07-18 10:54:39 -04:00
llvm.amdgcn.end.cf.i32.ll
[AMDGPU] Update VMEM scalar write hazard mitigation sequence
2020-07-16 11:37:45 +09:00
llvm.amdgcn.end.cf.i64.ll
AMDGPU/GlobalISel: Add pre-legalize combiner pass
2020-01-22 10:16:39 -05:00
llvm.amdgcn.fdot2.ll
AMDGPU/GlobalISel: Fix incorrect VOP3P fneg folding
2020-02-24 21:20:35 -05:00
llvm.amdgcn.fmul.legacy.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy
2020-02-21 10:30:26 -05:00
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.global.atomic.fadd.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.global.atomic.fadd
2020-08-12 10:04:53 -04:00
llvm.amdgcn.icmp.ll
AMDGPU/GlobalISel: Select icmp intrinsic
2020-06-30 10:57:41 +02:00
llvm.amdgcn.if.break.i32.ll
[AMDGPU] New SIInsertHardClauses pass
2020-05-14 18:54:49 +01:00
llvm.amdgcn.if.break.i64.ll
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.atomic.dim.ll
AMDGPU/GlobalISel: Handle image atomics
2020-03-30 17:41:04 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.gather4.dim.ll
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
llvm.amdgcn.image.gather4.o.dim.ll
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
llvm.amdgcn.image.getresinfo.a16.ll
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
llvm.amdgcn.image.getresinfo.ll
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
llvm.amdgcn.image.load.1d.d16.ll
[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer
2020-05-05 15:49:09 +01:00
llvm.amdgcn.image.load.1d.ll
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
llvm.amdgcn.image.load.2d.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.load.3d.a16.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.load.3d.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Avoid sorting stalls in regbank-reassign
2020-08-21 11:49:41 -07:00
llvm.amdgcn.image.sample.ltolz.a16.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.image.sample.ltolz.ll
AMDGPU/GlobalISel: Switch test to checking final ISA
2020-04-01 13:03:02 -04:00
llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] Better support for VMEM soft clauses in GCNHazardRecognizer
2020-05-05 15:49:09 +01:00
llvm.amdgcn.image.store.2d.ll
AMDGPU/GlobalISel: Start selecting image intrinsics
2020-03-30 17:33:04 -04:00
llvm.amdgcn.implicit.buffer.ptr.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.init.exec.ll
AMDGPU/GlobalISel: Select init_exec intrinsic
2020-07-01 11:50:59 +02:00
llvm.amdgcn.init.exec.wave32.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.interp.p1.f16.ll
AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16
2020-01-22 12:10:59 -05:00
llvm.amdgcn.is.private.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
llvm.amdgcn.is.shared.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU: Relax restriction on folding immediates into physregs
2020-07-29 14:01:53 -04:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU] New SIInsertHardClauses pass
2020-05-14 18:54:49 +01:00
llvm.amdgcn.mov.dpp8.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp8
2020-01-22 11:43:40 -05:00
llvm.amdgcn.permlane.ll
AMDGPU/GlobalISel: Select permlane16/permlanex16
2020-01-29 17:55:31 -05:00
llvm.amdgcn.queue.ptr.ll
AMDGPU/GlobalISel: Handle more input argument intrinsics
2019-07-01 18:50:50 +00:00
llvm.amdgcn.raw.buffer.atomic.add.ll
AMDGPU/GlobalISel: Select buffer atomics
2020-01-27 15:16:44 -05:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.buffer.atomic.cmpswap
2020-01-30 08:22:43 -05:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
AMDGPU: Define raw/struct variants of buffer atomic fadd
2020-08-06 13:36:19 -04:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
llvm.amdgcn.raw.buffer.load.format.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.load.format
2020-01-27 13:02:19 -05:00
llvm.amdgcn.raw.buffer.load.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
llvm.amdgcn.raw.buffer.store.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
llvm.amdgcn.raw.tbuffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.tbuffer.load
2020-01-27 13:40:37 -05:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping
2020-07-10 11:32:32 +02:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping
2020-07-10 11:32:32 +02:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping
2020-07-10 11:32:32 +02:00
llvm.amdgcn.rsq.clamp.ll
AMDGPU/GlobalISel: Implement expansion for rsq.clamp
2020-08-06 10:23:25 -04:00
llvm.amdgcn.s.buffer.load.ll
AMDGPU/GlobalISel: Ensure subreg is valid when selecting G_UNMERGE_VALUES
2020-08-04 12:27:34 -04:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.s.sleep.ll
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
llvm.amdgcn.sbfe.ll
[GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c'
2020-08-18 10:42:15 -07:00
llvm.amdgcn.sdot2.ll
AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting
2020-07-26 09:55:34 -04:00
llvm.amdgcn.sdot4.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.sdot8.ll
AMDGPU/GlobalISel: Fix incorrect VOP3P fneg folding
2020-02-24 21:20:35 -05:00
llvm.amdgcn.set.inactive.ll
AMDGPU/GlobalISel: Select set.inactive intrinsic
2020-07-24 10:14:14 +02:00
llvm.amdgcn.softwqm.ll
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
llvm.amdgcn.struct.buffer.atomic.add.ll
AMDGPU/GlobalISel: Select buffer atomics
2020-01-27 15:16:44 -05:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.buffer.atomic.cmpswap
2020-01-30 08:22:43 -05:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
AMDGPU: Define raw/struct variants of buffer atomic fadd
2020-08-06 13:36:19 -04:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.load.ll
AMDGPU/GlobalISel: Un-XFAIL a test
2020-02-25 16:46:46 +00:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.store[.format]
2020-01-27 15:00:21 -05:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
llvm.amdgcn.struct.tbuffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdcn.struct.tbuffer.load
2020-01-27 14:42:04 -05:00
llvm.amdgcn.trig.preop.ll
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
llvm.amdgcn.ubfe.ll
[GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c'
2020-08-18 10:42:15 -07:00
llvm.amdgcn.udot2.ll
AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting
2020-07-26 09:55:34 -04:00
llvm.amdgcn.udot4.ll
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
llvm.amdgcn.udot8.ll
AMDGPU/GlobalISel: Fix incorrect VOP3P fneg folding
2020-02-24 21:20:35 -05:00
llvm.amdgcn.update.dpp.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
llvm.amdgcn.workgroup.id.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.amdgcn.workitem.id.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.amdgcn.wqm.ll
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
llvm.amdgcn.wqm.vote.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.wqm.vote
2020-01-07 10:15:29 -05:00
llvm.amdgcn.writelane.ll
AMDGPU/GlobalISel: Manually select llvm.amdgcn.writelane
2020-08-11 11:56:16 -04:00
llvm.amdgcn.wwm.ll
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
llvm.powi.ll
GlobalISel: Legalize G_FPOWI
2020-07-21 18:13:04 -04:00
llvm.trap.ll
AMDGPU/GlobalISel: Support llvm.trap and llvm.debugtrap intrinsics
2020-03-05 08:16:57 +05:30
load-constant.96.ll
[AMDGPU] Reorganize GCN subtarget features for unaligned access
2020-08-21 12:26:31 +02:00
load-local.96.ll
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
load-local.128.ll
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
load-unaligned.ll
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
localizer.ll
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
lshr.ll
AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting
2020-07-26 09:55:34 -04:00
memory-legalizer-atomic-fence.ll
AMDGPU/GlobalISel: Select G_FENCE
2019-07-02 14:17:38 +00:00
minmaxabs.ll
[IR] Add min/max/abs intrinsics
2020-07-23 20:56:19 +02:00
mubuf-global.ll
AMDGPU: Fix not using scalar loads for global reads in shaders
2020-06-02 09:49:23 -04:00
mul.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
mul.v2i16.ll
AMDGPU/GlobalISel: Use packed for G_ADD/G_SUB/G_MUL v2s16
2020-02-25 11:20:35 -05:00
no-legalize-atomic.mir
AMDGPU/GlobalISel: Workaround some load/store type selection patterns
2020-06-15 07:42:20 -04:00
non-entry-alloca.ll
AMDGPU: Correct prolog SP initialization logic
2020-08-05 15:47:53 -04:00
orn2.ll
AMDGPU: Add flag to disable promotion of uniform i16 ops
2020-08-24 14:39:27 -04:00
postlegalizercombiner-select.mir
GlobalISel: fix CombinerHelper::matchEqualDefs()
2020-05-29 09:30:02 -07:00
read_register.ll
GlobalISel: Handle llvm.read_register
2020-01-09 17:37:52 -05:00
readcyclecounter.ll
AMDGPU/GlobalISel: Legalize G_READCYCLECOUNTER
2020-01-06 19:16:32 -05:00
regbankselect-add.s16.mir
AMDGPU/GlobalISel: Fix mishandling SGPR v2s16 add/sub/mul
2020-03-09 22:51:54 -04:00
regbankselect-add.s32.mir
AMDGPU/GlobalISel: Fix mishandling SGPR v2s16 add/sub/mul
2020-03-09 22:51:54 -04:00
regbankselect-add.v2s16.mir
AMDGPU/GlobalISel: Avoid illegal vector exts for add/sub/mul
2020-03-09 23:42:17 -04:00
regbankselect-amdgcn-exp-compr.mir
AMDGPU/GlobalISel: Fix RegBanKSelect for llvm.amdgcn.exp.compr
2020-01-23 13:30:46 -08:00
regbankselect-amdgcn-exp.mir
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
regbankselect-amdgcn-s-buffer-load.mir
AMDGPU/GlobalISel: Fix move s.buffer.load to VALU
2020-02-07 07:19:01 -08:00
regbankselect-amdgcn.ballot.i64.mir
AMDGPU/GlobalISel: Fix using readfirstlane with ballot intrinsics
2020-08-17 09:53:25 -04:00
regbankselect-amdgcn.class.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.cvt.pkrtz.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.div.fmas.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-amdgcn.div.scale.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.ds.append.mir
AMDGPU/GlobalISel: Select DS append/consume
2020-01-17 20:09:53 -05:00
regbankselect-amdgcn.ds.bpermute.mir
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
2019-06-29 00:33:13 +00:00
regbankselect-amdgcn.ds.consume.mir
AMDGPU/GlobalISel: Select DS append/consume
2020-01-17 20:09:53 -05:00
regbankselect-amdgcn.ds.gws.init.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.gws.sema.v.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.ordered.add.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.ordered.swap.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.ds.permute.mir
AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
2019-06-29 00:33:13 +00:00
regbankselect-amdgcn.ds.swizzle.mir
Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
2019-09-19 16:26:14 +00:00
regbankselect-amdgcn.else.32.mir
AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
2019-09-13 03:55:49 +00:00
regbankselect-amdgcn.else.64.mir
AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.else
2019-09-13 03:55:49 +00:00
regbankselect-amdgcn.fcmp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.fmul.legacy.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.groupstaticsize.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.icmp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-amdgcn.image.load.1d.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
regbankselect-amdgcn.image.sample.1d.ll
[AMDGPU] Add G16 support to image instructions
2020-06-12 11:26:31 +02:00
regbankselect-amdgcn.interp.mov.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p1.f16.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p1.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p2.f16.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.interp.p2.mir
AMDGPU/GlobalISel: RegBankSelect interp intrinsics
2020-01-22 09:01:34 -05:00
regbankselect-amdgcn.kernarg.segment.ptr.mir
…
regbankselect-amdgcn.kill.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-amdgcn.mfma.mir
AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics
2019-12-01 22:15:48 -08:00
regbankselect-amdgcn.ps.live.mir
AMDDGPU/GlobalISel: Fix RegBankSelect for llvm.amdgcn.ps.live
2020-01-20 23:21:53 -05:00
regbankselect-amdgcn.raw.buffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.raw.buffer.load
2020-01-27 12:49:23 -05:00
regbankselect-amdgcn.readfirstlane.mir
AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane
2019-07-01 16:19:39 +00:00
regbankselect-amdgcn.readlane.mir
AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands.
2020-08-24 17:54:34 -04:00
regbankselect-amdgcn.s.buffer.load.ll
GlobalISel: Reimplement moreElementsVectorDst
2020-08-03 09:03:48 -04:00
regbankselect-amdgcn.s.buffer.load.mir
AMDGPU/GlobalISel: Fix move s.buffer.load to VALU
2020-02-07 07:19:01 -08:00
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.getpc.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.getreg.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.memrealtime.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.memtime.mir
AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
2019-06-29 00:22:28 +00:00
regbankselect-amdgcn.s.sendmsg.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.s.sendmsghalt.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.struct.buffer.load.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.load
2020-01-27 13:05:55 -05:00
regbankselect-amdgcn.struct.buffer.store.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.struct.buffer.store[.format]
2020-01-27 15:00:21 -05:00
regbankselect-amdgcn.update.dpp.mir
AMDGPU/GlobalISel: RegBankSelect for update.dpp
2019-06-29 00:44:36 +00:00
regbankselect-amdgcn.wqm.mir
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
regbankselect-amdgcn.wqm.vote.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-amdgcn.writelane.mir
AMDGPU/GlobalISel: Copy type when inserting readfirstlane
2020-01-12 22:44:51 -05:00
regbankselect-amdgcn.wwm.mir
AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics
2020-01-24 13:06:44 -08:00
regbankselect-amdgpu-ffbh-u32.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-and-s1.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-and.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-anyext.mir
AMDGPU/GlobalISel: Fix splitting 64-bit extensions
2020-05-20 11:13:32 -04:00
regbankselect-ashr.mir
AMDGPU/GlobalISel: Fix RegBankSelect for v2s16 shifts
2020-04-11 20:55:33 -04:00
regbankselect-atomic-cmpxchg.mir
…
regbankselect-atomicrmw-add.mir
…
regbankselect-atomicrmw-and.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-fadd.mir
AMDGPU/GlobalISel: Handle G_ATOMICRMW_FADD
2019-08-01 03:33:15 +00:00
regbankselect-atomicrmw-max.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-min.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-or.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-sub.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-umax.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-umin.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-xchg.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-atomicrmw-xor.mir
AMDGPU/GlobalISel: Fix broken tests
2019-07-22 13:33:11 +00:00
regbankselect-bitcast.mir
GlobalISel: Verify G_BITCAST changes the type
2020-07-08 17:16:27 -04:00
regbankselect-bitreverse.mir
AMDGPU/GlobalISel: Select G_BITREVERSE
2019-09-04 20:46:31 +00:00
regbankselect-block-addr.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
regbankselect-brcond.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-bswap.mir
AMDGPU/GlobalISel: Handle G_BSWAP
2020-02-14 09:09:44 -08:00
regbankselect-build-vector-trunc.mir
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
2019-09-09 17:04:18 +00:00
regbankselect-build-vector-trunc.v2s16.mir
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
2020-02-05 11:52:18 -05:00
regbankselect-build-vector.mir
AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
2020-08-17 09:53:26 -04:00
regbankselect-concat-vector.mir
AMDGPU/GlobalISel: Start trying to handle AGPR bank
2020-08-06 12:39:50 -04:00
regbankselect-constant.mir
AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsics
2019-10-06 01:37:34 +00:00
regbankselect-copy.mir
AMDGPU/GlobalISel: Manually RegBankSelect copies
2020-03-11 11:12:12 -04:00
regbankselect-ctlz-zero-undef.mir
GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF
2020-02-09 19:02:38 -05:00
regbankselect-ctpop.mir
AMDGPU/GlobalISel: Split 64-bit G_CTPOP in RegBankSelect
2020-02-09 18:39:33 -05:00
regbankselect-cttz-zero-undef.mir
GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF
2020-02-09 19:02:38 -05:00
regbankselect-default.mir
GlobalISel: Enforce operand types for constants
2019-02-04 23:29:31 +00:00
regbankselect-dyn-stackalloc.mir
AMDGPU/GlobalISel: Handle uniform G_DYN_STACKALLOC
2020-06-03 19:56:07 -04:00
regbankselect-extract-vector-elt.mir
AMDGPU/GlobalISel: cmp/select method for extract element
2020-06-05 12:57:40 -07:00
regbankselect-extract.mir
AMDGPU/GlobalISel: Start trying to handle AGPR bank
2020-08-06 12:39:50 -04:00
regbankselect-fabs.mir
…
regbankselect-fadd.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fcanonicalize.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fceil.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fcmp.mir
…
regbankselect-fexp2.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-flog2.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fma.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fmul.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fneg.mir
…
regbankselect-fpext.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fptosi.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fptoui.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fptrunc.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-frame-index.mir
AMDGPU/GlobalISel: Assume VGPR for G_FRAME_INDEX
2019-10-02 01:02:24 +00:00
regbankselect-freeze.mir
AMDGPU/GlobalISel: Select G_FREEZE
2020-07-16 11:10:48 +02:00
regbankselect-frint.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fshr.mir
AMDGPU/GlobalISel: Basic legalize rules for G_FSHR
2020-03-30 11:53:01 -07:00
regbankselect-fsqrt.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-fsub.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-icmp.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-icmp.s16.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-illegal-copy.mir
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
2020-02-13 10:16:06 -08:00
regbankselect-insert-vector-elt.mir
AMDGPU/GlobalISel: cmp/select method for insert element
2020-06-10 13:12:54 -07:00
regbankselect-insert.mir
AMDGPU/GlobalISel: Start trying to handle AGPR bank
2020-08-06 12:39:50 -04:00
regbankselect-intrinsic-trunc.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-inttoptr.mir
…
regbankselect-load.mir
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
2020-06-15 11:33:16 -04:00
regbankselect-lshr.mir
AMDGPU/GlobalISel: Fix RegBankSelect for v2s16 shifts
2020-04-11 20:55:33 -04:00
regbankselect-merge-values.mir
AMDGPU/GlobalISel: Start trying to handle AGPR bank
2020-08-06 12:39:50 -04:00
regbankselect-mul.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-or.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-phi-s1.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-phi.mir
AMDGPU/GlobalISel: Start trying to handle AGPR bank
2020-08-06 12:39:50 -04:00
regbankselect-ptr-add.mir
[globalisel] Rename G_GEP to G_PTR_ADD
2019-11-05 10:31:17 -08:00
regbankselect-ptrmask.mir
GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic
2020-05-26 11:48:13 -04:00
regbankselect-ptrtoint.mir
GlobalISel: Verify pointer casts
2019-01-29 23:29:00 +00:00
regbankselect-reg-sequence.mir
Reapply "GlobalISel: Avoid producing Illegal copies in RegBankSelect"
2019-06-15 00:33:26 +00:00
regbankselect-sadde.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-select.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-sext-inreg.mir
AMDGPU/GlobalISel: Do a better job splitting 64-bit G_SEXT_INREG
2020-02-04 13:23:53 -08:00
regbankselect-sext.mir
AMDGPU/GlobalISel: Fix handling of G_ANYEXT with s1 source
2020-03-16 12:59:54 -04:00
regbankselect-sextload.mir
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
regbankselect-shl.mir
AMDGPU/GlobalISel: Fix RegBankSelect for v2s16 shifts
2020-04-11 20:55:33 -04:00
regbankselect-shuffle-vector.mir
AMDGPU/GlobalISel: Fix RegBankSelect for G_SHUFFLE_VECTOR
2020-02-17 15:11:25 -05:00
regbankselect-sitofp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-smax.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-smin.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-smulh.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-split-scalar-load-metadata.mir
CodeGen: Don't drop AA metadata when splitting MachineMemOperands
2020-08-20 16:17:30 -04:00
regbankselect-ssube.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-sub.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-trunc.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-uadde.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-uaddo.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-uitofp.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-umax.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-umin.mir
AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max
2020-02-21 14:02:16 -05:00
regbankselect-umulh.mir
AMDGPU/GlobalISel: Only map VOP operands to VGPRs
2020-01-30 08:32:35 -05:00
regbankselect-unmerge-values.mir
AMDGPU/GlobalISel: Start trying to handle AGPR bank
2020-08-06 12:39:50 -04:00
regbankselect-usube.mir
AMDGPU/GlobalISel: Fix forming G_TRUNC with vcc result
2020-01-31 20:29:41 -05:00
regbankselect-usubo.mir
AMDGPU/GlobalISel: Replace handling of boolean values
2020-01-06 18:26:42 -05:00
regbankselect-waterfall-agpr.mir
AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands.
2020-08-24 17:54:34 -04:00
regbankselect-xor.mir
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
2020-02-12 16:19:45 -08:00
regbankselect-zext.mir
AMDGPU/GlobalISel: Fix splitting 64-bit extensions
2020-05-20 11:13:32 -04:00
regbankselect-zextload.mir
AMDPGPU/GlobalISel: Select more MUBUF global addressing modes
2020-01-27 07:28:36 -08:00
regbankselect.mir
AMDGPU/GlobalISel: Start rewriting load/store legality rules
2020-06-06 09:59:46 -04:00
ret.ll
AMDGPU/GlobalISel: Handle most function return types
2019-07-26 02:36:05 +00:00
roundeven.ll
GlobalISel: Handle llvm.roundeven
2020-07-29 20:01:12 -04:00
saddsat.ll
GlobalISel: Revisit users of other merge opcodes in artifact combiner
2020-08-17 13:56:53 -04:00
sdiv.i32.ll
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
sdiv.i64.ll
[GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c'
2020-08-18 10:42:15 -07:00
shader-epilogs.ll
AMDGPU/GlobalISel: Remove unnecesssary REQUIREs
2019-05-29 13:14:35 +00:00
shl-ext-reduce.ll
AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr
2020-08-24 09:53:27 -04:00
shl.ll
AMDGPU/GlobalISel: Pack constant G_BUILD_VECTOR_TRUNCs when selecting
2020-07-26 09:55:34 -04:00
shlN_add.ll
AMDGPU/GlobalISel: Start matching s_lshlN_add_u32 instructions
2020-03-09 12:36:51 -07:00
smrd.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
srem.i32.ll
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
srem.i64.ll
[GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c'
2020-08-18 10:42:15 -07:00
ssubsat.ll
GlobalISel: Revisit users of other merge opcodes in artifact combiner
2020-08-17 13:56:53 -04:00
store-local.96.ll
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
store-local.128.ll
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
2020-08-21 12:26:31 +02:00
trunc.ll
GlobalISel: Implement fewerElementsVector for G_TRUNC
2020-03-10 15:17:20 -07:00
uaddsat.ll
[AMDGPU] Avoid sorting stalls in regbank-reassign
2020-08-21 11:49:41 -07:00
udiv.i32.ll
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
udiv.i64.ll
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
urem.i32.ll
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
urem.i64.ll
AMDGPU/GlobalISel: Sign extend integer constants
2020-07-26 09:30:14 -04:00
usubsat.ll
GlobalISel: Revisit users of other merge opcodes in artifact combiner
2020-08-17 13:56:53 -04:00
write_register.ll
GlobalISel: Lower G_WRITE_REGISTER
2020-01-29 06:48:24 -08:00
xnor.ll
Update AMDGPU testcases after bebe6a6449
2020-08-11 11:32:36 -07:00
zextload.ll
AMDGPU: Relax restriction on folding immediates into physregs
2020-07-29 14:01:53 -04:00
984a499f9d