forked from OSchip/llvm-project
97 lines
4.0 KiB
LLVM
97 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -O2 < %s | FileCheck %s -check-prefix=ENABLE
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; RUN: opt -S -hexagon-emit-lookup-tables=true -O2 < %s | FileCheck %s -check-prefix=ENABLE
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; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon-unknown--elf"
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; Function Attrs: noinline nounwind
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define i32 @foo(i32 %x) #0 section ".tcm_text" {
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; ENABLE-LABEL: @foo(
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; ENABLE-NEXT: entry:
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; ENABLE-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 6
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; ENABLE-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
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; ENABLE: switch.lookup:
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; ENABLE-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.foo, i32 0, i32 [[X]]
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; ENABLE-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
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; ENABLE-NEXT: br label [[RETURN]]
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; ENABLE: return:
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; ENABLE-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 19, [[ENTRY:%.*]] ]
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; ENABLE-NEXT: ret i32 [[RETVAL_0]]
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;
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; DISABLE-LABEL: @foo(
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; DISABLE-NEXT: entry:
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; DISABLE-NEXT: switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [
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; DISABLE-NEXT: i32 0, label [[RETURN:%.*]]
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; DISABLE-NEXT: i32 1, label [[SW_BB1:%.*]]
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; DISABLE-NEXT: i32 2, label [[SW_BB2:%.*]]
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; DISABLE-NEXT: i32 3, label [[SW_BB3:%.*]]
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; DISABLE-NEXT: i32 4, label [[SW_BB4:%.*]]
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; DISABLE-NEXT: i32 5, label [[SW_BB5:%.*]]
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; DISABLE-NEXT: ]
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; DISABLE: sw.bb1:
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; DISABLE-NEXT: br label [[RETURN]]
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; DISABLE: sw.bb2:
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; DISABLE-NEXT: br label [[RETURN]]
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; DISABLE: sw.bb3:
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; DISABLE-NEXT: br label [[RETURN]]
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; DISABLE: sw.bb4:
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; DISABLE-NEXT: br label [[RETURN]]
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; DISABLE: sw.bb5:
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; DISABLE-NEXT: br label [[RETURN]]
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; DISABLE: sw.default:
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; DISABLE-NEXT: br label [[RETURN]]
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; DISABLE: return:
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; DISABLE-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 19, [[SW_DEFAULT]] ], [ 5, [[SW_BB5]] ], [ 12, [[SW_BB4]] ], [ 22, [[SW_BB3]] ], [ 14, [[SW_BB2]] ], [ 20, [[SW_BB1]] ], [ 9, [[ENTRY:%.*]] ]
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; DISABLE-NEXT: ret i32 [[RETVAL_0]]
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;
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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switch i32 %0, label %sw.default [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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i32 3, label %sw.bb3
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i32 4, label %sw.bb4
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i32 5, label %sw.bb5
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]
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sw.bb: ; preds = %entry
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store i32 9, i32* %retval, align 4
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br label %return
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sw.bb1: ; preds = %entry
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store i32 20, i32* %retval, align 4
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br label %return
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sw.bb2: ; preds = %entry
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store i32 14, i32* %retval, align 4
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br label %return
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sw.bb3: ; preds = %entry
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store i32 22, i32* %retval, align 4
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br label %return
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sw.bb4: ; preds = %entry
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store i32 12, i32* %retval, align 4
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br label %return
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sw.bb5: ; preds = %entry
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store i32 5, i32* %retval, align 4
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br label %return
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sw.default: ; preds = %entry
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store i32 19, i32* %retval, align 4
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br label %return
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return: ; preds = %sw.default, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
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%1 = load i32, i32* %retval, align 4
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ret i32 %1
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}
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attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
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