forked from OSchip/llvm-project
101 lines
2.7 KiB
LLVM
101 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @t1(i16 zeroext %x, i32 %y) {
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; CHECK-LABEL: @t1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = zext i16 %x to i32
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 %y, 1
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; CHECK-NEXT: [[D:%.*]] = lshr i32 [[CONV]], [[TMP0]]
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; CHECK-NEXT: ret i32 [[D]]
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;
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entry:
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%conv = zext i16 %x to i32
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%s = shl i32 2, %y
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%d = sdiv i32 %conv, %s
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ret i32 %d
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}
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define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
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; CHECK-LABEL: @t1vec(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i32> [[Y:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[D:%.*]] = lshr <2 x i32> [[CONV]], [[TMP0]]
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; CHECK-NEXT: ret <2 x i32> [[D]]
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;
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entry:
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%conv = zext <2 x i16> %x to <2 x i32>
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%s = shl <2 x i32> <i32 2, i32 2>, %y
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%d = sdiv <2 x i32> %conv, %s
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ret <2 x i32> %d
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}
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; rdar://11721329
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define i64 @t2(i64 %x, i32 %y) {
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; CHECK-LABEL: @t2(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 %y to i64
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 %x, [[TMP1]]
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; CHECK-NEXT: ret i64 [[TMP2]]
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;
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%1 = shl i32 1, %y
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%2 = zext i32 %1 to i64
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%3 = udiv i64 %x, %2
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ret i64 %3
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}
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; PR13250
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define i64 @t3(i64 %x, i32 %y) {
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; CHECK-LABEL: @t3(
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 %y, 2
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 %x, [[TMP2]]
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; CHECK-NEXT: ret i64 [[TMP3]]
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;
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%1 = shl i32 4, %y
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%2 = zext i32 %1 to i64
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%3 = udiv i64 %x, %2
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ret i64 %3
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}
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define i32 @t4(i32 %x, i32 %y) {
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; CHECK-LABEL: @t4(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 %y, 5
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; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[TMP1]], i32 %y, i32 5
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 %x, [[DOTV]]
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%1 = shl i32 1, %y
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%2 = icmp ult i32 %1, 32
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%3 = select i1 %2, i32 32, i32 %1
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%4 = udiv i32 %x, %3
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ret i32 %4
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}
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define i32 @t5(i1 %x, i1 %y, i32 %V) {
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; CHECK-LABEL: @t5(
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; CHECK-NEXT: [[DOTV:%.*]] = select i1 %x, i32 5, i32 6
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 %V, [[DOTV]]
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; CHECK-NEXT: [[TMP2:%.*]] = select i1 %y, i32 [[TMP1]], i32 0
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%1 = shl i32 1, %V
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%2 = select i1 %x, i32 32, i32 64
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%3 = select i1 %y, i32 %2, i32 %1
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%4 = udiv i32 %V, %3
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ret i32 %4
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}
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define i32 @t6(i32 %x, i32 %z) {
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; CHECK-LABEL: @t6(
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; CHECK-NEXT: [[X_IS_ZERO:%.*]] = icmp eq i32 %x, 0
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; CHECK-NEXT: [[DIVISOR:%.*]] = select i1 [[X_IS_ZERO]], i32 1, i32 %x
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; CHECK-NEXT: [[Y:%.*]] = udiv i32 %z, [[DIVISOR]]
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; CHECK-NEXT: ret i32 [[Y]]
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;
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%x_is_zero = icmp eq i32 %x, 0
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%divisor = select i1 %x_is_zero, i32 1, i32 %x
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%y = udiv i32 %z, %divisor
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ret i32 %y
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}
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