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AsmParser
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[VE] Add vector mask operation instructions
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2020-10-29 08:42:41 +09:00 |
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Disassembler
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[VE] Fix initializer visibility
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2020-10-19 22:54:41 +01:00 |
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MCTargetDesc
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[VE] Fix initializer visibility
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2020-10-19 22:54:41 +01:00 |
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TargetInfo
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[VE] Fix initializer visibility
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2020-10-19 22:54:41 +01:00 |
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CMakeLists.txt
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[VE] Support a basic disassembler for Aurora VE target
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2020-06-03 13:48:42 +02:00 |
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LLVMBuild.txt
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[VE] Support a basic disassembler for Aurora VE target
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2020-06-03 13:48:42 +02:00 |
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VE.h
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[VE] Support convert instructions in MC layer
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2020-06-10 12:22:33 +02:00 |
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VE.td
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[VE] Add +vpu attribute
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2020-11-04 12:42:00 +01:00 |
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VEAsmPrinter.cpp
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[VE] Fix initializer visibility
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2020-10-19 22:54:41 +01:00 |
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VECallingConv.td
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[VE] Add v(m)regs to preserve_all reg mask
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2020-11-06 15:16:11 +01:00 |
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VEFrameLowering.cpp
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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VEFrameLowering.h
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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VEISelDAGToDAG.cpp
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[VE] Support register and frame-index pair correctly
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2020-10-05 18:36:53 +09:00 |
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VEISelLowering.cpp
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[VE][NFC] Refactor to support more than one calling conv
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2020-11-06 14:25:25 +01:00 |
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VEISelLowering.h
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[VE] Add +vpu attribute
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2020-11-04 12:42:00 +01:00 |
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VEInstrFormats.td
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[VE] Add VBRD/VMV instructions
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2020-10-19 18:33:54 +09:00 |
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VEInstrInfo.cpp
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[VE] Support f128
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2020-08-17 17:26:52 +09:00 |
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VEInstrInfo.h
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[VE] Add vector load/store instructions
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2020-10-15 09:26:55 +09:00 |
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VEInstrInfo.td
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[VE] Optimize address calculation
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2020-11-06 19:46:59 +09:00 |
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VEInstrVec.td
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[VE] Add vector control instructions
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2020-10-29 19:24:31 +09:00 |
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VEMCInstLower.cpp
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[VE] Support TargetBlockAddress
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2020-10-01 00:48:21 +09:00 |
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VEMachineFunctionInfo.cpp
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…
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VEMachineFunctionInfo.h
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…
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VERegisterInfo.cpp
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[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
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2020-11-05 11:02:18 +00:00 |
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VERegisterInfo.h
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[VE] Adapt aa26dd9858 and 2481f26ac3
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2020-04-07 15:45:19 -07:00 |
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VERegisterInfo.td
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[VE] Support register aliases in llvm-mc
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2020-10-29 23:28:32 +09:00 |
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VESubtarget.cpp
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[VE] Add +vpu attribute
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2020-11-04 12:42:00 +01:00 |
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VESubtarget.h
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[VE] Add +vpu attribute
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2020-11-04 12:42:00 +01:00 |
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VETargetMachine.cpp
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[VE] Support atomic load
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2020-10-26 18:02:45 +09:00 |
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VETargetMachine.h
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[VE] Target-specific bit size for sjljehprepare
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2020-03-10 17:51:16 +01:00 |
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VETargetTransformInfo.h
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[VE][TTI] don't advertise vregs/vops
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2020-11-06 11:12:10 +01:00 |
7914e4f0fa