Stanislav Mekhanoshin 3bffb1cd0e [AMDGPU] Use single cache policy operand ... Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469		2021-03-15 13:00:59 -07:00
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custom-pseudo-source-values.ll	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
expected-target-index-name.mir	…
intrinsics.mir	…
invalid-target-index-operand.mir	…
lit.local.cfg	…
llc-target-cpu-attr-from-cmdline-ir.mir	Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""	2020-11-11 14:40:14 +00:00
llc-target-cpu-attr-from-cmdline.mir	Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""	2020-11-11 14:40:14 +00:00
load-store-opt-dlc.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
load-store-opt-scc.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
machine-function-info-dynlds-align-invalid-case.mir	[amdgpu] Add codegen support for HIP dynamic shared memory.	2020-08-20 21:29:18 -04:00
machine-function-info-no-ir.mir	Make fixed-abi default for AMD HSA OS	2021-02-19 15:05:25 +00:00
machine-function-info-register-parse-error1.mir	…
machine-function-info-register-parse-error2.mir	…
machine-function-info.ll	AMDGPU: Add occupancy to serialized MachineFunctionInfo	2021-01-21 09:21:00 -05:00
mfi-frame-offset-reg-class.mir	…
mfi-parse-error-frame-offset-reg.mir	…
mfi-parse-error-scratch-rsrc-reg.mir	…
mfi-parse-error-stack-ptr-offset-reg.mir	…
mfi-scratch-rsrc-reg-reg-class.mir	…
mfi-stack-ptr-offset-reg-class.mir	…
mir-canon-multi.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
mircanon-memoperands.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
parse-order-reserved-regs.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
stack-id-assert.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
stack-id.mir	…
subreg-def-is-not-ssa.mir	MIR: Infer not-SSA for subregister defs	2020-08-27 16:56:16 -04:00
syncscopes.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
target-flags.mir	[AMDGPU] Fix offset for REL32_HI relocs	2020-09-02 10:55:55 +01:00
target-index-operands.mir	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00