forked from OSchip/llvm-project
96891f0418
This patch replaces the root-terminal vectorization approach implemented in the
Affine vectorizer with a topological order approach that vectorizes all the
operations within the target loop nest. These are the most important changes
introduced by the new algorithm:
* Removed tracking of root and terminal ops. Existing vectorization
functionality is preserved and extended so that loop nests without
root-terminal chains can be vectorized.
* Vectorizing a loop nest now only requires a single topological traversal.
* A new vector loop nest is incrementally built along the vectorization
process. The original scalar loop is kept intact. No cloning guard is needed
to recover the scalar loop if vectorization fails. This approach also
simplifies the challenging task of replacing a loop operation amid the
vectorization process without invalidating the analysis information that
depends on the original loop.
* Vectorization of specific operations has been implemented as independent,
preparing them to be moved to a potential vectorization interface.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D97442
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| .. | ||
| Analysis | ||
| Bindings | ||
| CAPI | ||
| Conversion | ||
| Dialect | ||
| EDSC | ||
| Examples | ||
| IR | ||
| Integration | ||
| Interfaces/DataLayoutInterfaces | ||
| Pass | ||
| Rewrite | ||
| SDBM | ||
| Target | ||
| Transforms | ||
| Unit | ||
| lib | ||
| mlir-cpu-runner | ||
| mlir-linalg-ods-gen | ||
| mlir-opt | ||
| mlir-reduce | ||
| mlir-rocm-runner | ||
| mlir-spirv-cpu-runner | ||
| mlir-tblgen | ||
| mlir-translate | ||
| mlir-vulkan-runner | ||
| APITest.h | ||
| CMakeLists.txt | ||
| lit.cfg.py | ||
| lit.site.cfg.py.in | ||