forked from OSchip/llvm-project
272 lines
12 KiB
C++
272 lines
12 KiB
C++
//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
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#include "AMDGPUISelLowering.h"
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#include "AMDGPUArgumentUsageInfo.h"
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#include "SIInstrInfo.h"
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namespace llvm {
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class SITargetLowering final : public AMDGPUTargetLowering {
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SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Chain, uint64_t Offset) const;
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SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
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SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
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const SDLoc &SL, SDValue Chain,
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uint64_t Offset, bool Signed,
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const ISD::InputArg *Arg = nullptr) const;
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SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
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const SDLoc &SL, SDValue Chain,
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const ISD::InputArg &Arg) const;
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SDValue getPreloadedValue(SelectionDAG &DAG,
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const SIMachineFunctionInfo &MFI,
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EVT VT,
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AMDGPUFunctionArgInfo::PreloadedValue) const;
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SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const override;
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SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
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MVT VT, unsigned Offset) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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/// \brief Converts \p Op, which must be of floating point type, to the
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/// floating point type \p VT, by either extending or truncating it.
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SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
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SDValue Op,
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const SDLoc &DL,
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EVT VT) const;
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SDValue convertArgType(
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SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
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bool Signed, const ISD::InputArg *Arg = nullptr) const;
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/// \brief Custom lowering for ISD::FP_ROUND for MVT::f16.
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SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
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SelectionDAG &DAG) const;
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SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
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void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
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SDValue performUCharToFloatCombine(SDNode *N,
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DAGCombinerInfo &DCI) const;
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SDValue performSHLPtrCombine(SDNode *N,
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unsigned AS,
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DAGCombinerInfo &DCI) const;
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SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
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SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
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unsigned Opc, SDValue LHS,
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const ConstantSDNode *CRHS) const;
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SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1) const;
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SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
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SDValue Op0, SDValue Op1, bool Signed) const;
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SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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unsigned getFusedOpcode(const SelectionDAG &DAG,
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const SDNode *N0, const SDNode *N1) const;
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SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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bool isLegalFlatAddressingMode(const AddrMode &AM) const;
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bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
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bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
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unsigned isCFIntrinsic(const SDNode *Intr) const;
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void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
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/// \returns True if fixup needs to be emitted for given global value \p GV,
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/// false otherwise.
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bool shouldEmitFixup(const GlobalValue *GV) const;
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/// \returns True if GOT relocation needs to be emitted for given global value
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/// \p GV, false otherwise.
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bool shouldEmitGOTReloc(const GlobalValue *GV) const;
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/// \returns True if PC-relative relocation needs to be emitted for given
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/// global value \p GV, false otherwise.
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bool shouldEmitPCReloc(const GlobalValue *GV) const;
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public:
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SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
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const SISubtarget *getSubtarget() const;
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bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
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unsigned IntrinsicID) const override;
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bool getAddrModeArguments(IntrinsicInst * /*I*/,
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SmallVectorImpl<Value*> &/*Ops*/,
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Type *&/*AccessTy*/) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool canMergeStoresTo(unsigned AS, EVT MemVT,
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const SelectionDAG &DAG) const override;
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
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unsigned Align,
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bool *IsFast) const override;
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsMemset,
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bool ZeroMemset,
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bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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bool isMemOpUniform(const SDNode *N) const;
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bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
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bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
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TargetLoweringBase::LegalizeTypeAction
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getPreferredVectorAction(EVT VT) const override;
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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bool supportSplitCSR(MachineFunction *MF) const override;
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void initializeSplitCSR(MachineBasicBlock *Entry) const override;
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void insertCopiesSplitCSR(
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MachineBasicBlock *Entry,
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const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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void passSpecialInputs(
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CallLoweringInfo &CLI,
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const SIMachineFunctionInfo &Info,
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SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
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SmallVectorImpl<SDValue> &MemOpChains,
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SDValue Chain,
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SDValue StackPtr) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
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SDValue ThisVal) const;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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unsigned getRegisterByName(const char* RegName, EVT VT,
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SelectionDAG &DAG) const override;
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MachineBasicBlock *splitKillBlock(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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bool enableAggressiveFMAFusion(EVT VT) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
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void AdjustInstrPostInstrSelection(MachineInstr &MI,
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SDNode *Node) const override;
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SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
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MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
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SDValue Ptr) const;
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MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
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uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
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SDValue V) const;
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void finalizeLowering(MachineFunction &MF) const override;
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};
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} // End namespace llvm
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#endif
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